DAC3482_15 Datasheet, PDF (57/106 Pages) Texas Instruments – DAC3482, Dual-Channel, 16-Bit, 1.25 GSPS Digital-to-Analog Converter (DAC)

www.ti.com
DAC3482
SLAS748F – MARCH 2011 – REVISED AUGUST 2015
IOUTP
IOUTN
100 Ω
4:1
AGND
100 Ω
R_LOAD
50 Ω
S0518-01
Figure 86. Driving a Doubly Terminated 50-Ω Cable Using a 4:1 Impedance Ratio Transformer
7.4 Device Functional Modes
7.4.1 Multi-Device Synchronization
In various applications, such as multi antenna systems where the various transmit channels information is
correlated, it is required that multiple DAC devices are completely synchronized such that their outputs are phase
aligned. The DAC3482 architecture supports this mode of operation.
7.4.1.1 Multi-Device Synchronization: PLL Bypassed with Dual Sync Sources Mode
For single or multi-device synchronization it is important that delay differences in the data are absorbed by the
device so that latency through the device remains the same. Furthermore, to ensure that the outputs from each
DAC are phase aligned it is necessary that data is read from the FIFO of each device simultaneously. In the
DAC3482 this is accomplished by operating the multiple devices in Dual Sync Sources mode. In this mode the
additional OSTR signal is required by each DAC3482 to be synchronized.
Data into the device is input as LVDS signals from one or multiple baseband ASICs or FPGAs. Data into the
multiple DAC devices can experience different delays due to variations in the digital source output paths or board
level wiring. These different delays can be effectively absorbed by the DAC3482 FIFO so that all outputs are
phase aligned correctly.
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: DAC3482
Submit Documentation Feedback
57