LM3S5C56 Datasheet, PDF (877/1146 Pages) Texas Instruments – Stellaris® LM3S5C56 Microcontroller

Stellaris^® LM3S5C56 Microcontroller
Bit/Field
4
3
2
1
0
Name
ERROR
SETUP
STALLED
TXRDY
RXRDY
Type
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
Description
Error
Value Description
0 No error.
1 Three attempts have been made to perform a transaction with
no response from the peripheral. The EP0 bit in the USBTXIS
register is also set in this situation.
Software must clear this bit.
Setup Packet
Value Description
0 Sends an OUT token.
1 Sends a SETUP token instead of an OUT token for the
transaction. This bit should be set at the same time as the
TXRDY bit is set.
Setting this bit always clears the DT bit in the USBCSRH0 register to
send a DATA0 packet.
Endpoint Stalled
Value Description
0 No handshake has been received.
1 A STALL handshake has been received.
Software must clear this bit.
Transmit Packet Ready
Value Description
0 No transmit packet is ready.
1 Software sets this bit after loading a data packet into the TX
FIFO. The EP0 bit in the USBTXIS register is also set in this
situation.
If both the TXRDY and SETUP bits are set, a setup packet is
sent. If just TXRDY is set, an OUT packet is sent.
This bit is cleared automatically when the data packet has been
transmitted.
Receive Packet Ready
Value Description
0 No received packet has been received.
1 Indicates that a data packet has been received in the RX FIFO.
The EP0 bit in the USBTXIS register is also set in this situation.
Software must clear this bit after the packet has been read from the
FIFO to acknowledge that the data has been read from the FIFO.
January 23, 2012
877
Texas Instruments-Production Data