DP83816EX Datasheet, PDF (87/108 Pages) Texas Instruments – DP83816EX 10/100 Mb/s Integrated PCI Ethernet Media Access Controller and Physical Layer (MacPhyter-II)Extended Temperature Range 0 to 85 Degrees C

rxDescRefr
CR:RXE && CRDD
XferDone
link = NULL
rxIdle
rxAdvance
link != NULL
CR:RXE && !CRDD
XferDone && OWN
rxDescRead
XferDone
rxDescWrite
rxPktBytes == 0
rxFifoBlock
XferDone && !OWN
FifoReady
rxFragWrite
(descCnt == 0) && (rxPktBytes > 0)
XferDone
Figure 5-7 Receive State Diagram
5.3.2 Receive Data Flow
With a bus mastering architecture, some number of buffers
and descriptors for received packets must be pre-allocated
when the DP83816-EX is initialized. The number allocated
will directly affect the system's tolerance to interrupt
latency. The more buffers that you pre-allocate, the longer
the system will survive an incoming burst without losing
receive packets, if receive descriptor processing is delayed
or preempted. Buffers sizes should be allocated in 32 byte
multiples.
1. Prior to packet reception, receive buffers must be
described in a receive descriptor list (or ring, if
preferred). In each descriptor, the driver assigns
ownership to the hardware by clearing the OWN bit.
Receive descriptors may describe a single buffer.
2. The address of the first descriptor in this list is then
written to the RXDP register. As packets arrive, they
are placed in available buffers. A single packet may
occupy one or more receive descriptors, as required
by the application.The device reads in the first
descriptor into the RxDescCache.
3. As data arrives in the RxDataFIFO, the receive buffer
management state machine places the data in the
receive buffer described by the descriptor. This
continues until either the end of packet is reached, or
the descriptor byte count for this descriptor is
reached.
4. If end of packet was reached, the status in the
descriptor (in main memory) is updated by setting the
OWN bit and clearing the MORE bit, by updating the
receive status bits as indicated by the MAC, and by
updating the SIZE field. The status bits in cmdsts are
only valid in the last descriptor of a packet (with the
MORE bit clear). Also for the last descriptor of a
packet, the SIZE field will be updated to reflect the
actual amount of data written to the buffer (which
may be less the full buffer size allocated by the
descriptor).
If the receive buffer management state machine runs out of
descriptors while receiving a packet, data will buffer in the
receive FIFO. If the FIFO overflows, the driver will be
interrupted with an RxOVR error.
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