DP83816EX Datasheet, PDF (84/108 Pages) Texas Instruments – DP83816EX 10/100 Mb/s Integrated PCI Ethernet Media Access Controller and Physical Layer (MacPhyter-II)Extended Temperature Range 0 to 85 Degrees C

5.2.2 Transmit Data Flow
In the DP83816-EX transmit architecture, packet
transmission involves the following steps:
1. The device driver receives packets from an upper
layer.
2. An available DP83816-EX transmit descriptor is
allocated. The fragment information is copied from
the NOS specific data structure(s) to the DP83816-
EX transmit descriptor.
3. The driver adds this descriptor to it’s internal list of
transmit descriptors awaiting transmission and sets
the OWN bit.
4. If the internal list was empty (this descriptor
represents the only outstanding transmit packet),
then the driver must set the TXDP register to the
address of this descriptor, else the driver will append
this descriptor to the end of the list.
5. The driver sets the TXE bit in the CR register to insure
that the transmit state machine is active.
6. If idle, the transmit state machine reads the descriptor
into the TxDescriptorCache.
7. The state machine then moves through the fragment
described within the descriptor, filling the TxDataFifo
with data. The hardware handles all aspects of byte
alignment; no alignment is assumed. Fragments
may start and/or end on any byte address. The
transmit state machine uses the fragment pointer
and the SIZE field from the cmdsts field of the current
descriptor to keep the TxDataFifo full. It also uses the
MORE bit and the SIZE field from the cmdsts field of
the current descriptor to know when packet
boundaries occur.
8. When a packet has completed transmission
(successful or unsuccessful), the state machine
updates the upper half of the cmdsts field of the
current descriptor in main memory, relinquishing
ownership, and indicating the packet completion
status. This update is done by a bus master
transaction that transfers only the upper 2 bytes to
the descriptor being updated. If more than one
descriptor was used to describe the packet, then
completion status is updated only in the last
descriptor. Intermediate descriptors only have the
OWN bits modified.
9. If the link field of the descriptor is non-zero, the state
machine advances to the next descriptor and
continues.
10. If the link field is NULL, the transmit state machine
suspends, waiting for the TXE bit in the CR register
to be set. If the TXDP register is written to, the CTDD
flag will be cleared. When the TXE bit is set, the state
machine will examine CTDD. If CTDD is set, the
state machine will "refresh" the link field of the
current descriptor. It will then follow the link field to
any new descriptors that have been added to the end
of the list. If CTDD is clear (implying that TXDP has
been written to), the state machine will start by
reading in the descriptor pointed to by TXDP.
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