AM3352BZCZ100 Datasheet, PDF (85/236 Pages) Texas Instruments – Sitara AM335x ARM Cortex-A8 Microprocessors (MPUs)

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SPRS717F – OCTOBER 2011 – REVISED APRIL 2013
Table 3-9. VDD_CORE Operating Performance Points for ZCE Package
with Device Revision Code "A" or Newer⁽¹⁾
VDD_CORE
VDD_MPU⁽²⁾
OPP
Rev "A" or
MIN
newer
NOM
MAX
ARM (A8)
DDR3,
DDR3L⁽³⁾
DDR2⁽³⁾
mDDR⁽³⁾
L3 and L4
OPP100
1.056 V
1.100 V
1.144 V
600 MHz
400 MHz
266 MHz
200 MHz 200 MHz and
100 MHz
OPP100
1.056 V
1.100 V
1.144 V
300 MHz
400 MHz
266 MHz
200 MHz 200 MHz and
100 MHz
OPP50
0.912 V
0.950 V
0.988 V
300 MHz
-
125 MHz
90 MHz 100 MHz and
50 MHz
(1) Frequencies in this table indicate maximum performance for a given OPP condition.
(2) VDD_MPU is merged with VDD_CORE on the ZCE package.
(3) This parameter represents the maximum memory clock frequency. Since data is transferred on both edges of the clock, double-data rate
(DDR), the maximum data rate is two times the maximum memory clock frequency defined in this table.
Copyright © 2011–2013, Texas Instruments Incorporated
Device Operating Conditions
85
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