SMV320C6727B-SP_16 Datasheet, PDF (83/112 Pages) Texas Instruments – Floating-Point Digital Signal Processor

SMV320C6727B-SP
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SPRS675G – FEBRUARY 2013 – REVISED JANUARY 2014
4.14.3 SPI Electrical Data/Timing
4.14.3.1 Serial Peripheral Interface (SPI) Timing
Table 4-27 through Table 4-34 assume testing over recommended operating conditions (see Figure 4-33
through Figure 4-36).
Table 4-27. General Timing Requirements for SPIx Master Modes⁽¹⁾
NO.
PARAMETER
1 t_c(SPC)M
2 t_w(SPCH)M
3 t_w(SPCL)M
Cycle Time, SPIx_CLK, All Master Modes
Pulse Width High, SPIx_CLK, All Master Modes
Pulse Width Low, SPIx_CLK, All Master Modes
Polarity = 0, Phase = 0,
to SPIx_CLK rising
Delay, initial data bit ^{Polarity = 0, Phase = 1,}
4
t_{d(SIMO_SPC)M}
valid on SPIx_SIMO to
initial edge on
SPIx_CLK ⁽²⁾
to SPIx_CLK rising
Polarity = 1, Phase = 0,
to SPIx_CLK falling
Polarity = 1, Phase = 1,
to SPIx_CLK falling
Polarity = 0, Phase = 0,
from SPIx_CLK rising
Delay, subsequent bits ^{Polarity = 0, Phase = 1,}
5
t_{d(SPC_SIMO)M}
valid on SPIx_SIMO
after transmit edge of
from SPIx_CLK falling
Polarity = 1, Phase = 0,
SPIx_CLK
from SPIx_CLK falling
Polarity = 1, Phase = 1,
from SPIx_CLK rising
Polarity = 0, Phase = 0,
from SPIx_CLK falling
Output hold time,
Polarity = 0, Phase = 1,
SPIx_SIMO valid after _{from SPIx_CLK rising}
6 t_{oh(SPC_SIMO)M} receive edge of
SPIxCLK, except for
Polarity = 1, Phase = 0,
final bit⁽³⁾
from SPIx_CLK rising
Polarity = 1, Phase = 1,
from SPIx_CLK falling
Polarity = 0, Phase = 0,
to SPIx_CLK falling
Input Setup Time,
7
t_{su(SOMI_SPC)M}
SPIx_SOMI valid
before receive
edge of SPIx_CLK
Polarity = 0, Phase = 1,
to SPIx_CLK rising
Polarity = 1, Phase = 0,
to SPIx_CLK rising
Polarity = 1, Phase = 1,
to SPIx_CLK falling
Polarity = 0, Phase = 0,
from SPIx_CLK falling
Input Hold Time,
Polarity = 0, Phase = 1,
8
t_{ih(SPC_SOMI)M}
SPIx_SOMI valid after
receive edge of
from SPIx_CLK rising
Polarity = 1, Phase = 0,
SPIx_CLK
from SPIx_CLK rising
Polarity = 1, Phase = 1,
from SPIx_CLK falling
MIN
greater of 8P or 100 ns
greater of 4P or 45 ns
greater of 4P or 45 ns
2P
0.5t_c(SPC)M + 2P
2P
0.5t_c(SPC)M + 2P
0.5t_c(SPC)M – 10
0.5t_c(SPC)M – 10
0.5t_c(SPC)M – 10
0.5t_c(SPC)M – 10
0.5P + 15
0.5P + 15
0.5P + 15
0.5P + 15
0.5P + 5
0.5P + 5
0.5P + 5
0.5P + 5
TYP
MAX UNIT
256P ns
ns
ns
ns
15
15
ns
15
15
ns
ns
ns
(1) P = SYSCLK2 period
(2) First bit may be MSB or LSB depending upon SPI configuration. MO(0) refers to first bit and MO(n) refers to last bit output on
SPIx_SIMO. MI(0) refers to the first bit input and MI(n) refers to the last bit input on SPIx_SOMI.
(3) The final data bit will be held on the SPIx_SIMO pin until the SPIDAT0 or SPIDAT1 register is written with new data.
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Peripheral and Electrical Specifications
83
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