TPS659037 Datasheet, PDF (82/96 Pages) Texas Instruments – Power Management Unit (PMU)

TPS659037
SLIS165C – DECEMBER 2014 – REVISED NOVEMBER 2015
www.ti.com
7 Power Supply Recommendations
The TPS659037 device is designed to work with an analog supply voltage range of 3.135 V to 5.25 V. The
input supply should be well regulated and connected to the VCC1 pin, as well as SMPS and LDO input
pins with appropriate bypass capacitors as recommended in Figure 6-1. If the input supply is located more
than a few inches from the TPS659037 device, additional capacitance may be required in addition to the
recommended input capacitors at the VCC1 pin and the SMPS and LDO input pins.
8 Layout
8.1 Layout Guidelines
As in every switch-mode-supply design, the following general layout rules apply:
• Use a solid ground-plane for power-ground (PGND)
• Use an independent ground for Logic, LDOs and Analog (AGND)
• Connect those Grounds at a star-point ideally underneath the device.
• Place input capacitors as close as possible to the input-pins of the device. This is paramount and more
important than the output-loop!
• Place the inductor and output capacitor as close as possible to the phase node (or switch-node) of the
device.
• Keep the loop-area formed by Phase-node, Inductor, output-capacitor and PGND as small as possible.
• For traces and vias on power-lines, keep inductance and resistance as small as possible by using wide
traces, avoid switching layers but if needed, use plenty of vias.
The goal of the previously listed guidelines is a layout that minimizes emissions, maximizes EMI-immunity,
and maintains a safe operating area for the device.
To minimize the spiking at the phase-node for both, high-side (VIN – SWx) as well as low-side (SWx –
PGND), the decoupling of VIN is paramount. Appropriate decoupling and thorough layout should ensure
that the spikes never exceed 9-V peak-to-peak at the device.
TI recommends the guidelines shown in Figure 8-1 regarding parasitic inductance and resistance.
Parasitic Inductance: < 1 nH
Parasitic resistance: < 3 PŸ
Parasitic resistance:
As small as possible to
get best efficiency
Parasitic inductance: < 1 nH
Parasitic resistance: < 2 PŸ
SMPSx_IN
SMPSx_SW
SMPSx_SW
Connection to power plane
Parasitic resistance:
As small as possible to get best
efficiency
SMPSx_GND
Parasitic inductance: < 1 nH
Parasitic resistance: < 2 PŸ
For multiple
capacitors, keep the
parasitic resistance as
small as possible
among capacitors
82
Layout
Figure 8-1. Parasitic Inductance and Resistance
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