TPS659037 Datasheet, PDF (26/96 Pages) Texas Instruments – Power Management Unit (PMU)

TPS659037
SLIS165C – DECEMBER 2014 – REVISED NOVEMBER 2015
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I²C Interface Timing Requirements (continued)
over operating free-air temperature range, typical values are at T_A = 27°C (unless otherwise noted)^(1)(2)(3)(4).
MIN
t_r(CL)
t_r(CL1)
t_f(CL)
t_r(DA)
t_f(DA)
Rise time of the SCL signal
Rise time of the SCL signal after
a REPEATED START condition
and after an Acknowledge bit
Fall time of the SCL signal
Rise time of the SDA signal
Fall time of the SDA signal
Standard mode
Fast mode
High-speed mode, C_B – 100 pF maximum
High-speed mode, C_B – 400 pF maximum
Standard mode
Fast mode
High-speed mode, C_B – 100 pF maximum
High-speed mode, C_B – 400 pF maximum
Standard mode
Fast mode
High-speed mode, C_B – 100 pF maximum
High-speed mode, C_B – 400 pF maximum
Standard mode
Fast mode
High-speed mode, C_B – 100 pF maximum
High-speed mode, C_B – 400 pF maximum
Standard mode
Fast mode
High-speed mode, C_B – 100 pF maximum
High-speed mode, C_B – 400 pF maximum
Standard mode
20 + 0.1 C_B
20 + 0.1 C_B
10
20
20 + 0.1 C_B
20 + 0.1 C_B
10
20
20 + 0.1 C_B
20 + 0.1 C_B
10
20
20 + 0.1 C_B
20 + 0.1 C_B
10
20
20 + 0.1 C_B
20 + 0.1 C_B
10
20
4
t_su(STOP)
Setup time for a STOP condition Fast mode
600
High-speed mode
160
C_B
Capacitive load for SDA and
SCL
MAX
1000
300
40
80
1000
300
80
160
300
300
40
80
1000
300
80
160
300
300
80
160
400
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
pF
4.20 SPI Timing Requirements
See Figure 4-3
t_su(ce)
t_h(ce)
t_c(clk)
t_{p(HIGH_ck)}
t_{p(LOW_ck)}
t_su(si)
t_h(si)
t_dr
t_(CE)
Chip-select set up time
Chip-select hold time
Clock cycle time
Clock high typical pulse duration
Clock low typical pulse duration
Input data set up time, before clock active edge
Input data hold time, after clock active edge
Data retention time
Time from CE going low to CE going high
Capacitive load on pin SDO
MIN
MAX UNIT
30
ns
30
ns
67
100
ns
20
ns
20
ns
5
ns
5
ns
15
ns
67
ns
30
pF
SDA
t_f
t_(LOW)
t_r
t_su(DAT)
t_f
t_h(STA)
t_r
t_(buf)
SCL
S
t_h(STA)
t_h(DAT)
t_(HIGH)
t_su(STA)
Sr
t_su(STO)
P
S
Figure 4-1. Serial Interface Timing Diagram for F/S Mode
26
Specifications
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