TMS320C6455_17 Datasheet, PDF (82/256 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

TMS320C6455
SPRS276M – MAY 2005 – REVISED MARCH 2012
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4.4 Bus Priorities
On the C6455 device, bus priority is programmable for each master. The register bit fields and default
priority levels for C6455 bus masters are shown in Table 4-2. The priority levels should be tuned to obtain
the best system performance for a particular application. Lower values indicate higher priorities. For some
masters, the priority values are programmed at the system level by configuring the PRI_ALLOC register.
Details on the PRI_ALLOC register are shown in Figure 4-3. The C64x+ megamodule , SRIO, and EDMA
masters contain registers that control their own priority values.
The priority is enforced when several masters in the system are vying for the same endpoint. Note that the
configuration SCR port on the data SCR is considered a single endpoint meaning priority will be enforced
when multiple masters try to access the configuration SCR. Priority is also enforced on the configuration
SCR side when a master (through the data SCR) tries to access the same endpoint as the C64x+
megamodule.
In the PRI_ALLOC register, the HOST field applies to the priority of the HPI and PCI peripherals. The
EMAC field specifies the priority of the EMAC peripheral. The SRIO field is used to specify the priority of
the Serial RapidIO when accessing descriptors from system memory. The priority for Serial RapidIO data
accesses is set in the peripheral itself.
Table 4-2. C6455 Default Bus Master Priorities
BUS MASTER
EDMA3TC0
EDMA3TC1
EDMA3TC2
EDMA3TC3
SRIO (Data Access)
SRIO (Descriptor Access)
EMAC
PCI
HPI
C64x+ Megamodule (MDMA port)
DEFAULT
PRIORITY LEVEL
PRIORITY CONTROL
0
QUEPRI.PRIQ0 (EDMA3 register)
0
QUEPRI.PRIQ1 (EDMA3 register)
0
QUEPRI.PRIQ2 (EDMA3 register)
0
QUEPRI.PRIQ3 (EDMA3 register)
0
PER_SET_CNTL.CBA_TRANS_PRI
(SRIO register)
0
PRI_ALLOC.SRIO
1
PRI_ALLOC.EMAC
2
PRI_ALLOC.HOST
2
PRI_ALLOC.HOST
7
MDMAARBE.PRI (C64x+ Megamodule
Register)
31
Reserved
R-0000 0000 0000 0000
15
12
11
9
8
6
Reserved
SRIO
Reserved
R-000 0
R/W-001
R-100
LEGEND: R/W = Read/Write; R = Read only; -n = value at reset
5
3
HOST
R/W-010
Figure 4-3. Priority Allocation Register (PRI_ALLOC)
16
2
0
EMAC
R/W-001
82
System Interconnect
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