LM3S9781_15 Datasheet, PDF (816/1271 Pages) Texas Instruments – Stellaris LM3S9781 Microcontroller

Inter-Integrated Circuit Sound (I²S) Interface
The basic programming model of the I²S block is as follows:
■ Configuration
– Overall I²S module configuration in the I²S Module Configuration (I2SCFG) register. This
register is used to select the MCLK source and enable the receiver and transmitter.
– Transmit and receive configuration in the I²S Transmit Module Configuration (I2STXCFG)
and I²S Receive Module Configuration (I2SRXCFG) registers. These registers set the basic
parameters for the receiver and transmitter such as data configuration (justification, delay,
read mode, sample size, and system data size); SCLK (polarity and source); and word select
polarity.
– Transmit and receive FIFO configuration in the I²S Transmit FIFO Configuration
(I2STXFIFOCFG) and I²S Receive FIFO Configuration (I2SRXFIFOCFG) registers. These
registers select the Compact Stereo mode size (16-bit or 8-bit), provide indication of whether
the next sample is Left or Right, and select mono mode for the receiver.
■ FIFO
– Transmit and receive FIFO data in the I²S Transmit FIFO Data (I2STXFIFO) and I²S Receive
FIFO Data (I2SRXFIFO) registers
– Information on FIFO data levels in the I²S Transmit FIFO Level (I2STXLEV) and I²S Receive
FIFO Level (I2SRXLEV) registers
– Configuration for FIFO service requests based on FIFO levels in the I²S Transmit FIFO Limit
(I2STXLIMIT) and I²S Receive FIFO Limit (I2SRXLIM) registers
■ Interrupt Control
– Interrupt masking configuration in the I²S Interrupt Mask (I2SIM) register
– Raw and masked interrupt status in the I²S Raw Interrupt Status (I2SRIS) and I²S Masked
Interrupt Status (I2SMIS) registers
– Interrupt clearing through the I²S Interrupt Clear (I2SIC) register
– Configuration for FIFO service requests interrupts and transmit/receive error interrupts in the
I²S Transmit Interrupt Status and Mask (I2STXISM) and I²S Receive Interrupt Status
and Mask (I2SRXISM) registers
Figure 16-2 on page 817 provides an example of an I²S data transfer. Figure 16-3 on page 817
provides an example of an Left-Justified data transfer. Figure 16-4 on page 817 provides an example
of an Right-Justified data transfer.
816
July 03, 2014
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