TM4C1233H6PZIR Datasheet, PDF (808/1233 Pages) Texas Instruments – Tiva TM4C1233H6PZ Microcontroller

Analog-to-Digital Converter (ADC)
Register 3: ADC Interrupt Mask (ADCIM), offset 0x008
This register controls whether the sample sequencer and digital comparator raw interrupt signals
are sent to the interrupt controller. Each raw interrupt signal can be masked independently.
Note:
Only a single DCONSSn bit should be set at any given time. Setting more than one of these
bits results in the INRDC bit from the ADCRIS register being masked, and no interrupt is
generated on any of the sample sequencer interrupt lines. It is recommended that when
interrupts are used, they are enabled on alternating samples or at the end of the sample
sequence.
ADC Interrupt Mask (ADCIM)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x008
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
DCONSS3 DCONSS2 DCONSS1 DCONSS0
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
MASK3 MASK2 MASK1 MASK0
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:20
19
Name
reserved
DCONSS3
Type
RO
R/W
Reset
0x000
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Digital Comparator Interrupt on SS3
Value Description
0 The status of the digital comparators does not affect the SS3
interrupt status.
1 The raw interrupt signal from the digital comparators (INRDC
bit in the ADCRIS register) is sent to the interrupt controller on
the SS3 interrupt line.
18
DCONSS2
R/W
0
Digital Comparator Interrupt on SS2
Value Description
0 The status of the digital comparators does not affect the SS2
interrupt status.
1 The raw interrupt signal from the digital comparators (INRDC
bit in the ADCRIS register) is sent to the interrupt controller on
the SS2 interrupt line.
808
July 17, 2013
Texas Instruments-Production Data