TM4C1233H6PZIR Datasheet, PDF (509/1233 Pages) Texas Instruments – Tiva TM4C1233H6PZ Microcontroller

Tiva^™ TM4C1233H6PZ Microcontroller _{(identical to LM4F122H5QC)}
8.2.2.3
8.2.2.4
8.2.3
8.2.3.1
8.2.3.2
Host or On-The-Go (OTG) applications on Tiva™ C Series microcontroller-based boards (for more
information, see the TivaWare™ USB Library for C Series User's Guide (literature number
SPMU297)).
Advanced Encryption Standard (AES) Cryptography Tables
AES is a strong encryption method with reasonable performance and size. AES is fast in both
hardware and software, is fairly easy to implement, and requires little memory. AES is ideal for
applications that can use pre-arranged keys, such as setup during manufacturing or configuration.
Four data tables used by the XySSL AES implementation are provided in the ROM. The first is the
forward S-box substitution table, the second is the reverse S-box substitution table, the third is the
forward polynomial table, and the final is the reverse polynomial table. See the TM4C1233H6PZ
ROM User’s Guide for more information on AES.
Cyclic Redundancy Check (CRC) Error Detection
The CRC technique can be used to validate correct receipt of messages (nothing lost or modified
in transit), to validate data after decompression, to validate that Flash memory contents have not
been changed, and for other cases where the data needs to be validated. A CRC is preferred over
a simple checksum (e.g. XOR all bits) because it catches changes more readily. See the
TM4C1233H6PZ ROM User’s Guide for more information on CRC.
Flash Memory
At system clock speeds of 40 MHz and below, the Flash memory is read in a single cycle. The Flash
memory is organized as a set of 1-KB blocks that can be individually erased. An individual 32-bit
word can be programmed to change bits from 1 to 0. In addition, a write buffer provides the ability
to program 32 continuous words in Flash memory in half the time of programming the words
individually. Erasing a block causes the entire contents of the block to be reset to all 1s. The 1-KB
blocks are paired into sets of 2-KB blocks that can be individually protected. The protection allows
blocks to be marked as read-only or execute-only, providing different levels of code protection.
Read-only blocks cannot be erased or programmed, protecting the contents of those blocks from
being modified. Execute-only blocks cannot be erased or programmed and can only be read by the
controller instruction fetch mechanism, protecting the contents of those blocks from being read by
either the controller or a debugger.
Prefetch Buffer
The Flash memory controller has a prefetch buffer that is automatically used when the CPU frequency
is greater than 40 MHz. In this mode, the Flash memory operates at half of the system clock. The
prefetch buffer fetches two 32-bit words per clock allowing instructions to be fetched with no wait
states while code is executing linearly. The fetch buffer includes a branch speculation mechanism
that recognizes a branch and avoids extra wait states by not reading the next word pair. Also, short
loop branches often stay in the buffer. As a result, some branches can be executed with no wait
states. Other branches incur a single wait state.
Flash Memory Protection
The user is provided two forms of Flash memory protection per 2-KB Flash memory block in four
pairs of 32-bit wide registers. The policy for each protection form is controlled by individual bits (per
policy per block) in the FMPPEn and FMPREn registers.
■ Flash Memory Protection Program Enable (FMPPEn): If a bit is set, the corresponding block
may be programmed (written) or erased. If a bit is cleared, the corresponding block may not be
changed.
July 17, 2013
509
Texas Instruments-Production Data