TAS5782M Datasheet, PDF (80/128 Pages) Texas Instruments – 30 W Stereo Class-D Amplifier with 96-kHz Processing

TAS5782M
SLASEG8 – MARCH 2017
www.ti.com
Figure 92. Register 3 (0x03)
7
6
5
4
3
2
1
Reserved
RQML
Reserved
RO
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
0
RQMR
R/W
Table 29. Register 3 (0x03) Field Descriptions
Bit Field
7-5 Reserved
4
RQML
3-1 Reserved
0
RQMR
Type
RO
R/W
Reset
0
R/W
R/W 0
Description
Reserved
Mute Left Channel – This bit issues soft mute request for the left channel. The volume
will be smoothly ramped down/up to avoid pop/click noise.
0: Normal volume
1: Mute
Reserved
Mute Right Channel – This bit issues soft mute request for the right channel. The
volume will be smoothly ramped down/up to avoid pop/click noise.
0: Normal volume
1: Mute
Figure 93. Register 4 (0x04)
7
6
5
4
3
2
1
Reserved
PLCK
Reserved
R/W
R
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
0
PLLE
R
Bit Field
7-5 Reserved
4
PLCK
3-1 Reserved
0
PLLE
Table 30. Register 4 (0x04) Field Descriptions
Type
R/W
R
Reset
0
R/W
R
1
Description
Reserved
PLL Lock Flag – This bit indicates whether the PLL is locked or not. When the PLL is
disabled this bit always shows that the PLL is not locked.
0: The PLL is locked
1: The PLL is not locked
Reserved
PLL Enable – This bit enables or disables the internal PLL. When PLL is disabled, the
master clock will be switched to the MCLK.
0: Disable PLL
1: Enable PLL
13.1.2 Register 6 (0x06)
Figure 94. Register 6 (0x06)
7
6
5
4
Reserved
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
3
DBPG
R/W
2
1
0
Reserved
R/W
Bit Field
7-4 Reserved
Type
Table 31. Register 6 (0x06) Field Descriptions
Reset
0
Description
Reserved
80
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