TAS5782M Datasheet, PDF (45/128 Pages) Texas Instruments – 30 W Stereo Class-D Amplifier with 96-kHz Processing

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TAS5782M
SLASEG8 – MARCH 2017
9.3.3.5 Serial Audio Port – Data Formats and Bit Depths
The serial audio interface port is a 3-wire serial port with the signals LRCK/FS (pin 25), SCLK (pin 23), and SDIN
(pin 24). SCLK is the serial audio bit clock, used to clock the serial data present on SDIN into the serial shift
register of the audio interface. Serial data is clocked into the TAS5782M device on the rising edge of SCLK. The
LRCK/FS pin is the serial audio left/right word clock or frame sync when the device is operated in TDM Mode.
FORMAT
I²S/LJ/RJ
TDM
Table 7. TAS5782M Audio Data Formats, Bit Depths and Clock Rates
DATA BITS
32, 24, 20, 16
32, 24, 20, 16
MAXIMUM LRCK/FS
FREQUENCY (kHz)
Up to 96
Up to 48
96
MCLK RATE (f_S)
128 to 3072 (≤ 50 MHz)
128 to 3072
128 to 512
SCLK RATE (f_S)
64, 48, 32
125, 256
125, 256
The TAS5782M device requires the synchronization of LRCK/FS and system clock, but does not require a
specific phase relation between LRCK/FS and system clock.
If the relationship between LRCK/FS and system clock changes more than ±5 MCLK, internal operation is
initialized within one sample period and analog outputs are forced to the bipolar zero level until re-
synchronization between LRCK/FS and system clock is completed.
If the relationship between LRCK/FS and SCLK are invalid more than 4 LRCK/FS periods, internal operation is
initialized within one sample period and analog outputs are forced to the bipolar zero level until re-
synchronization between LRCK/FS and SCLK is completed.
9.3.3.5.1 Data Formats and Master/Slave Modes of Operation
The TAS5782M device supports industry-standard audio data formats, including standard I²S and left-justified.
Data formats are selected via Register (P0-R40). All formats require binary two's complement, MSB-first audio
data; up to 32-bit audio data is accepted. The data formats are detailed in Figure 68 through Figure 73.
The TAS5782M device also supports right-justified, and TDM data. I²S, LJ, RJ, and TDM are selected using
Register (P0-R40). All formats require binary 2s complement, MSB-first audio data. Up to 32 bits are accepted.
Default setting is I²S and 24 bit word length. The I²S slave timing is shown in Figure 20.
shows a detailed timing diagram for the serial audio interface.
In addition to acting as a I²S slave, the TAS5782M device can act as an I²S master, by generating SCLK and
LRCK/FS as outputs from the MCLK input. Table 8 lists the registers used to place the device into Master or
Slave mode. Please refer to the Serial Audio Port Timing – Master Mode section for serial audio Interface timing
requirements in Master Mode. For Slave Mode timing, please refer to the Serial Audio Port Timing – Slave Mode
section.
P0-R9-B0, B4, and B5
P0-R32-D[6:0]
P0-R33-D[7:0]
REGISTER
Table 8. I²S Master Mode Registers
I²S Master mode select
FUNCTION
SCLK divider and LRCK/FS divider
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