TSC2013-Q1 Datasheet, PDF (8/70 Pages) Texas Instruments – TSC2013-Q1 12-Bit, Nanopower, 4-Wire Dual-Touch Screen Controller With I2C Interface

TSC2013-Q1
SLVSC89A – JUNE 2014 – REVISED JULY 2014
www.ti.com
6.8 Timing Requirements — I²C High-Speed Mode (ƒ_(SCL) = 1.7 MHz)
All specifications typical at –40°C to 125°C, V_{(SNSVDD/VREF)} = V_(I/OVDD) = to 3 V, unless otherwise noted.
MIN
t_{(WL_RESET)} Reset low time ⁽¹⁾
See Figure 2 and Figure 37
10
ƒ_(SCL)
SCL clock frequency
t_h(STA)
Hold time of (repeated) START condition
160
t_(LOW)
Low period of SCL clock
320
t_(HIGH)
High period of the SCL clock
See Figure 2
120
t_su(STA)
Setup time for a repeated START condition
160
t_h(DAT)
Data hold time
0
t_su(DAT)
Data setup time
10
t_r(CL)
Rise time of SCL signal
20
t_r(DA)
Rise time of SDA signal
20
t_f(CL)
Fall time of SCL signal
C_(b) = total bus capacitance⁽²⁾
20
t_f(DA)
Fall time of SDA signal
Figure 2
1
t_r(CL1)
Rise time of SCL signal after a repeated START
condition and after an acknowledge bit
20
t_su(STO)
Setup time for STOP condition
See Figure 2
160
C_(b)
Capacitive load for each bus line
C_(b) = total capacitance of one bus line in pF
t_d(SP)
Pulse duration of spikes that must be
suppressed by the input filter
0
(1) V_{(SNSVDD/VREF)} ≥ 1.6 V
(2) For capacitive bus loads between 100 pF and 400 pF, interpolate the rise-time and fall-time values linearly.
MAX
1.7
150
80
160
80
160
160
400
10
UNIT
μs
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
ns
6.9 Timing Requirements — I²C High-Speed Mode (ƒ_(SCL) = 3.4 MHz)
All specifications typical at –40°C to 125°C, V_{(SNSVDD/VREF)} = V_(I/OVDD) = 1.6 V⁽¹⁾ to 3 V, unless otherwise noted.
MIN
t_{(WL_RESET)} Reset low time ⁽²⁾
See Figure 2 and Figure 37
10
ƒ_(SCL)
SCL clock frequency
t_h(STA)
Hold time for (repeated) START condition
160
t_(LOW)
Low period of SCL clock
160
t_(HIGH)
High period of the SCL clock
See Figure 2
60
t_su(STA)
Setup time for a repeated START condition
160
t_h(DAT)
Data hold time
0
t_su(DAT)
Data setup time
10
t_r(CL)
Rise time of SCL signal
10
t_r(DA)
Rise time of SDA signal
10
t_f(CL)
Fall time of SCL signal
C_(b) = total bus capacitance⁽³⁾
10
t_f(DA)
Fall time of SDA signal
See Figure 2
1
t_r(CL1)
Rise time of SCL signal after a repeated START
condition and after an acknowledge bit
10
t_su(STO)
Setup time for STOP condition
See Figure 2
160
C_(b)
Capacitive load for each bus line
C_(b) = total capacitance of one bus line in pF
t_d(SP)
Pulse duration of spikes that must be
suppressed by the input filter
0
MAX
3.4
70
40
80
40
80
80
100
10
UNIT
μs
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
ns
(1) Because of the low supply voltage of 1.2 V and the wide temperature range of –40°C to 125°C, the I²C system devices may not reach
the maximum specification of I²C high-speed mode, and ƒ_(SCL) may not reach 3.4 MHz.
(2) V_{(SNSVDD/VREF)} ≥ 1.6 V
(3) Capacitive load from 10 pF to 100 pF.
8
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