TSC2013-Q1 Datasheet, PDF (31/70 Pages) Texas Instruments – TSC2013-Q1 12-Bit, Nanopower, 4-Wire Dual-Touch Screen Controller With I2C Interface

www.ti.com
TSC2013-Q1
SLVSC89A – JUNE 2014 – REVISED JULY 2014
Programming (continued)
7.5.1.2 I²C High-Speed Mode (Hs Mode)
Serial data transfer format in high-speed (Hs) mode meets the fast or standard (F-S) mode I²C bus specification.
Hs mode can only commence after the following conditions (all of which are in F-S mode) exist:
1. Start condition (S)
2. 8-bit master code (0000 1xxx)
3. Not-acknowledge bit (N)
Figure 32 shows this sequence in more detail. Hs-mode master codes are reserved 8-bit codes used only for
triggering Hs mode. Do not use these codes for slave addressing or any other purpose. The master code
indicates to other devices that an Hs-mode transfer is about to begin and the connected devices must meet the
Hs mode specification. Because no device can acknowledge the master code, a not-acknowledge bit (N) follows
the master code.
After the not-acknowledge bit (N) and SCL achieve a high level, the master switches to Hs-mode and enables (at
time t_(H); shown in Figure 32) the current-source pullup circuit for SCL. Because other devices can delay the
serial transfer before t_(H) by stretching the LOW period of SCL, the master enables the current-source pullup
circuit when all devices have released SCL and SCL has reached a high level, thus speeding up the last part of
the rise time of the SCL.
The master then sends a repeated start condition (Sr) followed by a 7-bit slave address with an R/W bit address,
and receives an acknowledge bit (A) from the selected slave. After a repeated start (Sr) condition and after each
acknowledge bit (A) or not-acknowledge bit (N), the master disables the current-source pullup circuit. This
disabling enables other devices to delay the serial transfer by stretching the low period of SCL. The master re-
enables the current-source pullup circuit again when all devices have released, and SCL reaches a high level,
which speeds up the last part of the SCL signal rise time.
Data transfer continues in Hs mode after the next repeated start (Sr), and only switches back to F-S mode after a
stop condition (P). To reduce the overhead of the master code, the master can link to a number of Hs mode
transfers, separated by repeated start conditions (Sr).
S
8-Bit Master Code 00001xxx
N
t_H
SDA
SCL
1
2 to 5
6
7
8
9
Fast or Standard Mode
Sr
7-Bit Slave Address
R/W A
SDA
n x (8-Bit DATA + A/N)
Sr P
SCL
t_H
1
2 to 5
67 89
1 2 to 5 6 7 8 9
High-Speed Mode
= Current-Source Pull Up
= Resistor Pull Up
A = Acknowledge (SDA LOW)
N = Not Acknowledge (SDA HIGH)
S = START Condition
P = STOP Condition
Sr = Repeated START Condition
If P then
Fast or Standard Mode
If Sr (dashed lines
)
then High-Speed Mode
t_FS
Figure 32. Complete High-Speed Mode Transfer
Copyright © 2014, Texas Instruments Incorporated
Submit Documentation Feedback
31