TLC5733 Datasheet, PDF (8/23 Pages) Texas Instruments – 20 MSPS 3-CHANNEL ANALOG-TO-DIGITAL CONVERTER

TLC5733A
20 MSPS 3ĆCHANNEL ANALOGĆTOĆDIGITAL CONVERTER
WITH HIGHĆPRECISION CLAMP
SLAS104B − JULY 1995 − REVISED FEBRUARY 2001
clamp voltages and selection (continued)
Table 2. Clamp Level (Internal Connection Level)
CLPEN
L
H
CONDITION
EXTCLP
L
COMPOSITE SYNC input
NT/PAL
Don’t Care
Don’t Care
L
H
FUNCTION (EACH ADC)
INTERNAL CLAMP
CLAMP PULSE
Inactive
External clamp pulse
Inactive
No clamping
Active
Synchronous with NTSC
Active
Synchronous with PAL
The clamp circuit is shown in Figure 6. The clamp voltage is stored on capacitor C2 during the back porch of
the horizontal blanking period.
During the clamp pulse the input to channel A is clamped to:
V_C(A) = (16/256) × (voltage difference from terminal RT A to RB A)
V_C(B) = (128/256) × (voltage difference from terminal RT B to RB B)
V_C(C) = (128/256) × (voltage difference from terminal RT C to RB C)
COMPOSITE SYNC time monitoring
When CLPEN is high, COMPOSITE SYNC generates an internal clamp pulse on the horizontal blanking interval
back porch. The TLC5733A has a timing window into which the horizontal sync tip must occur. There is a noise
time window for the falling edge and one for the rising edge (see Figure 1, Figure 2, and Table 3).
correct COMPOSITE SYNC timing
The noise gate 1 signal provides the timing window for the COMPOSITE SYNC falling edge. After an interval
A of 867 clocks for NTSC or 1075 for PAL from the last falling edge of COMPOSITE SYNC, noise gate 1 signal
goes high for 43 clocks for NTSC or 61 clocks for PAL (interval B). The falling edge of the input signal to the
EXTCLP terminal can occur at any time within this window to be a valid COMPOSITE SYNC falling edge.
The noise gate 2 signal provides the timing window for the COMPOSITE SYNC rising edge. On the falling edge
of the horizontal sync tip, the internal logic generates noise gate 2 as a low signal for 58 clocks (interval C) for
both NTSC and PAL and then returns to a high active state. At this time if the input to EXTCLP is still low, it is
considered a valid COMPOSITE SYNC signal.
normal clamp pulse generation
On the rising edge of COMPOSITE SYNC, the internal logic generates an internal delay (interval D) and then
generates the internal positive clamp pulse 54 clocks wide (interval F).
clamp operation with incorrect COMPOSITE SYNC timing
noise suppression
If the input to EXTCLP goes low prior to noise gate 1 going high (within 43 clocks for NTSC or 61 clocks for PAL
of the normal 1H timing for the falling edge of COMPOSITE SYNC) then that input is not considered a valid
COMPOSITE SYNC and is ignored.
If the input to EXTCLP is high when noise gate 2 goes to the high state, the input signal is considered noise and
is ignored.
Therefore, the correct signal must be high for a maximum of 43 clocks for NTSC or 61 clocks for PAL, before
the 1H timing, to be a valid sync signal. Also, the input to EXTCLP must be at least 58 clocks wide (interval C)
to be valid.
This function of monitoring the timing eliminates spurious noise spikes from falsely synchronizing the system.
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