TLC5733 Datasheet, PDF (4/23 Pages) Texas Instruments – 20 MSPS 3-CHANNEL ANALOG-TO-DIGITAL CONVERTER

TLC5733A
20 MSPS 3ĆCHANNEL ANALOGĆTOĆDIGITAL CONVERTER
WITH HIGHĆPRECISION CLAMP
SLAS104B − JULY 1995 − REVISED FEBRUARY 2001
Terminal Functions
TERMINAL
NAME
NO.
A AVCC
AD8 −AD1
62
6 −13
AIN
63
B AVCC
BD8 −BD1
51
17 −24
BIN
50
C AVCC
CD8 −CD1
30
36 −43
CIN
31
CLK
56
CLPEN
57
CLP OUT A
59
CLP OUT B
54
CLP OUT C
27
CLPV A
60
CLPV B
53
CLPV C
28
DGND
15
DVDD
26
EXTCLP
55
GND A
64
GND B
49
GND C
32
INIT
58
MODE0
46
MODE1
45
NT/ PAL
3
OE A
2
OE B
47
I/O
DESCRIPTION
I Analog supply voltage of ADC A
O Data output of ADC A (LSB: AD1, MSB:AD8)
I Analog input of ADC A
I Analog supply voltage of ADC B
O Data output of ADC B (LSB: BD1, MSB:BD8)
I Analog input of ADC B
I Analog supply voltage of ADC C
O Data output of ADC C (LSB:CD1, MSB: CD8)
When MODE0 = L, MODE1 = L, CD8 outputs MSB flag of BD8 −BD5
When MODE0 = L, MODE1 = L, CD7 outputs MSB flag of BD8 −BD5
When MODE0 = L, MODE1 = H, CD8 outputs B channel flag of CD8 −BD1
When MODE0 = L, MODE1 = H, CD8 outputs B channel flag of CD8 −BD1
I Analog input of ADC C
I Clock input. The clock frequency is normally 4 × the frequency subcarrier (fsc) for most video systems (see
Table 3). The nominal clock frequency is 14.31818 MHz for National Television System Committee (NTSC)
and 17.745 MHz for phase alteration line (PAL).
I Clamp enable. When using an internal clamp pulse, CLPEN should be high. When using an external clamp
pulse, CLPEN should be low.
O Clamping bias current of ADC A. A resistor-capacitor combination that sets the clamp timing.
O Clamping bias current of ADC B. A resistor-capacitor combination that sets the clamp timing.
O Clamping bias current of ADC C. A resistor-capacitor combination that sets the clamp timing.
O Clamping level of ADC A. A capacitor is connected to CLPV A to set the clamp timing. The clamp level at
CLPV A is connected to an output code of 16 (0010000).
O Clamping level of ADC B. A capacitor is connected to CLPV B to set the clamp timing. The clamp level at
CLPV B is connected to an output code of 128 (1000000).
O Clamping level of ADC C. A capacitor is connected to CLPV C to set the clamp timing. The clamp level at
CLPV C is connected to an output code of 128 (1000000).
I Digital ground
I Digital supply voltage
I External clamp pulse input. When EXTCLP and CLPEN are low, the internal clamp circuit cannot be used.
The external clamp pulse when used is active high.
I Ground of ADC A
I Ground of ADC B
I Ground of ADC C
I Output initialized. The output data is synchronous when INIT is taken high from low. INIT is a control terminal
that allows the external system to initialize the TLC5733A data conversion cycle. INIT is usually used at
power up or system reset.
I Output format mode selector 0. When MODE1 is low and MODE0 is low, output data format1 is selected.
When MODE1 is low and MODE0 is high, output data format2 is selected. When MODE1 is high and
MODE0 is low, output data format3 is selected. A high level on MODE1 and a high level on MODE0 is not
used.
I Output format mode selector 1. When MODE1 is low and MODE0 is low, output data format1 is selected.
When MODE1 is low and MODE0 is high, output data format2 is selected. When MODE1 is high and
MODE0 is low, output data format3 is selected. A high level on MODE1 and a high level on MODE0 is not
used.
I NTSC/PAL control. NTSC/PAL should be low for NTSC and high for PAL.
I Output enable A. OE A enables the output of ADC A.
I Output enable B. OE B enables the output of ADC B.
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