TL7660_14 Datasheet, PDF (8/23 Pages) Texas Instruments – CMOS VOLTAGE CONVERTER

TL7660
CMOS VOLTAGE CONVERTER
SCAS794 – JUNE 2006
www.ti.com
APPLICATION INFORMATION (continued)
Theoretical Power Efficiency Considerations
In theory, a voltage converter can approach 100% efficiency if certain conditions are met.
• The driver circuitry consumes minimal power.
• The output switches have extremely low ON resistance and virtually no offset.
• The impedances of the pump and reservoir capacitors are negligible at the pump frequency.
The TL7660 approaches these conditions for negative voltage conversion if large values of C₁ and C₂ are used.
Energy is only lost in the transfer of charge between capacitors if a change in voltage occurs. The energy lost is
defined by:
E = ½ C₁(V₁₂ – V₂₂)
Where V₁ and V₂ are the voltages on C₁ during the pump and transfer cycles. If the impedances of C₁ and C₂
are relatively high at the pump frequency (see Figure 2) compared to the value of R_L, there is a substantial
difference in the voltages V₁ and V₂. Therefore, it is not only desirable to make C₂ as large as possible to
eliminate output voltage ripple but also to employ a correspondingly large value for C₁ in order to achieve
maximum efficiency of operation.
Do's and Don'ts
• Do not exceed maximum supply voltages.
• Do not connect LV terminal to GND for supply voltages greater than 3.5 V.
• Do not short circuit the output to V_CC supply for supply voltages above 5.5 V for extended periods, however,
transient conditions including start-up are okay.
• When using polarized capacitors, the positive terminal of C₁ must be connected to terminal 2 of the TL7660,
and the positive terminal of C₂ must be connected to GND.
• If the voltage supply driving the TL7660 has a large source impedance (25 Ω – 30 Ω), then a 2.2-µF
capacitor from terminal 8 to ground may be required to limit rate of rise of input voltage to less than 2V/µs.
• Ensure that the output (terminal 5) does not go more positive than GND (terminal 3). Device latch up occurs
under these conditions. A 1N914 or similar diode placed in parallel with C₂ prevents the device from latching
up under these conditions (anode to terminal 5, cathode to terminal 3).
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