TAS5760L Datasheet, PDF (8/77 Pages) Texas Instruments – Check for Samples: TAS5760L

TAS5760L
SLOS782B – JULY 2013 – REVISED SEPTEMBER 2015
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
T_A
AVDD
PVDD
DVDD
VIH_(DR)
VIL_(DR)
R_{SPK (BTL)}
R_{SPK (PBTL)}
Ambient Operating Temperature
AVDD Supply
PVDD Supply
DVDD Supply
Input Logic HIGH for DVDD Referenced Digital Inputs
Input Logic LOW for DVDD Referenced Digital Inputs
Minimum Speaker Load in BTL Mode
Minimum Speaker Load in PBTL Mode
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MIN
NOM
–25
4.5
4.5
2.8
DVDD
0
4
2
MAX
85
16.5
16.5
3.63
UNIT
°C
V
V
V
V
V
Ω
Ω
7.4 Thermal Information
TAS5760L
THERMAL METRIC⁽¹⁾
DCA
[HTSSOP]
32-PIN ⁽²⁾
DCA
[HTSSOP]
48-PIN ⁽²⁾
DAP
[HTSSOP]
32-PIN ⁽³⁾
DAP
[HTSSOP]
48-PIN ⁽³⁾
UNIT
θ_JA Junction-to-ambient thermal resistance
θ_JC(top) Junction-to-case (top) thermal resistance
θ_JB Junction-to-board thermal resistance
ψ_JT Junction-to-top characterization parameter
ψ_JB Junction-to-board characterization parameter
θ_{JC(bott Junction-to-case (bottom) thermal resistance}
om)
60.3
30.2
60.3
31.9
°C/W
16
14.3
16
16
°C/W
12
12.7
12
17
°C/W
0.4
0.6
0.4
0.4
°C/W
11.9
12.7
11.9
16.8
°C/W
0.8
0.7
0.8
0.81
°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) JEDEC Standard 2 Layer Board
(3) JEDEC Standard 4 Layer Board
7.5 Digital I/O Pins
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
V_IH1
Input Logic HIGH threshold for DVDD
Referenced Digital Inputs
All digital pins
V_IL1
Input Logic LOW threshold for DVDD
Referenced Digital Inputs
All digital pins
I_IH1
Input Logic HIGH Current Level
I_IL1
Input Logic LOW Current Level
V_OH Output Logic HIGH Voltage Level
V_OL Output Logic LOW Voltage Level
All digital pins
All digital pins
I_OH = 2 mA
I_OH = -2 mA
MIN
TYP
MAX UNIT
70
%DVDD
30 %DVDD
15
µA
–15
µA
90
%DVDD
10 %DVDD
7.6 Master Clock
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
D_MCLK
Allowable MCLK Duty Cycle
MCLK Input Frequency
f_MCLK
Supported single-speed MCLK
Frequencies
Supported double-speed MCLK
Frequencies
Values: 64, 128, 192, 256, 384,
and 512
Values: 64, 128, and 256
MIN
45%
64
64
TYP
50%
MAX
55%
25
512
256
UNIT
MHz
x f_s
8
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