LP2994_14 Datasheet, PDF (8/19 Pages) Texas Instruments – DDR Termination Regulator

Block Diagram
Obsolete Device
Description
The LP2994 is a linear bus termination regulator designed to
meet the JEDEC requirements of SSTL-2 and SSTL-3. The
output, V_TT is capable of sinking and sourcing current while
regulating the output voltage equal to V_DDQ / 2. The output
stage has been designed to maintain excellent load regulation
while preventing shoot through. The LP2994 also incorpo-
rates two distinct power rails which separates the analog
circuitry from the power output stage. This allows a split rail
approach to be utilized to decrease internal power dissipation.
It also permits the LP2994 to provide a termination solution
for the next generation of DDR-SDRAM memory (DDRII).
Series Stub Termination Logic (SSTL) was created to im-
prove signal integrity of the data transmission across the
memory bus. This termination scheme is essential to prevent
data error from signal reflections while transmitting at high
frequencies encountered with DDR-SDRAM. The most com-
mon form of termination is Class II single parallel termination.
This involves one R_S series resistor from the chipset to the
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memory and one R_T termination resistor. Typical values for
R_S and R_T are 25 Ohms, although these can be changed to
scale the current requirements from the LP2994. This imple-
mentation can be seen below in Figure 2.
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FIGURE 2. SSTL Termination Scheme
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