LP2994_14 Datasheet, PDF (2/19 Pages) Texas Instruments – DDR Termination Regulator

Obsolete Device
LP2994
March 28, 2011
DDR Termination Regulator
General Description
The LP2994 regulator is designed to provide a linear solution
to meet the JEDEC SSTL-2 and SSTL-3 specifications (Se-
ries Stub Termination Logic) for active termination of DDR-
SDRAM. The device utilizes an internal operational amplifier
to provide linear regulation of V_TT without the need for expen-
sive external components. The output stage prevents shoot
through while delivering 1.5A continuous current and main-
taining excellent load regulation. The LP2994 also incorpo-
rates an active low shutdown pin to tri-state the output during
Suspend To Ram (STR) states.
Patents Pending
Features
■ ^{Source and sink current}
■ ^{Low external component count}
■ ^{Independent analog and power rails}
■ ^{Linear topology}
■ ^{Small package SO-8}
■ ^{Low cost and easy to use}
■ ^{Shutdown pin}
Applications
■ ^SSTL-2
■ ^SSTL-3
■ ^{DDR-SDRAM Termination}
■ ^{DDR-II Termination}
Typical Application Circuit
FIGURE 1. SSTL-2 V_TT Termination
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