LMP92018_14 Datasheet, PDF (8/34 Pages) Texas Instruments – LMP92018 Analog System Monitor and Controller

LMP92018
SNAS514B – NOVEMBER 2011 – REVISED MAY 2013
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Electrical Characteristics (continued)
Unless otherwise noted, these specifications apply for VDD=4.75V to 5.25V, REF=VDD, T_A=25°C. Boldface limits are over
the temperature range of −30°C ≤ T_A ≤ 85°C unless otherwise noted. DAC input code range 12 to 1012. DAC output
C_L = 200 pF unless otherwise noted.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DIGITAL INPUT CHARACTERISTICS (CSB, DIN, SCLK)
V_IH
Input HIGH Voltage
V_IL
Input LO Voltage
Hysteresis
0.7 x VIO
V
0.3 x VIO
V
250
mV
I_IND
Digital Input Current
C_IND
Input Capacitance
DIGITAL OUTPUT CHARACTERISTICS (GPIO[11:0])
±0.005
±1
µA
4
pF
V_OL
Output LO Voltage
I_OUT = 200 µA
I_OUT = 1.6 mA
VGPIO = VDD = 5V
0.01
0.4
V
0.07
0.4
I_OUT = 200µA
VGPIO-0.2
V_OH
Output HI Voltage
I_OUT = 1.6 mA
VGPIO = VDD = 5V
VGPIO-0.5
V
IOZH, IOZL
TRI-STATE Output Leakage
Current
VGPIO=VDD
±5
µA
C_OUT
Output Capacitance
DIGITAL OUTPUT CHARACTERISTICS (DOUT)
4
pF
V_OL
Output LO Voltage
I_OUT = 200 µA
I_OUT = 1.6 mA
VIO = 3.3V
0.01
0.4
V
0.07
0.6
V
I_OUT = 200 µA
VIO-0.2
V_OH
Output HI Voltage
I_OUT = 1.6 mA
VIO = 3.3V
VIO-0.5
V
IOZH, IOZL
TRI-STATE Output Leakage
Current
VGPIO = 1.8V =VDD
±5
µA
C_OUT
Output Capacitance
DIGITAL OUTPUT CHARACTERISTICS (DRDYB)
4
pF
V_{OH_MAX} Maximum Output HI Voltage
I_OUT = 1.6 mA
VIO = 3.3V to VDD
VIO-0.5
µA
V_OL
Output LO Voltage
POWER SUPPLY CHARACTERISTICS
Force 0V or VDD
0.01
V
V_DD
V_GPIO
V_IO
I_DD
PWR_CONV
Supply Voltage Range
GPIO Rail Range
SPI Rail Range
Supply Current, Conversion Mode
Power Consumption, Conversion
Mode
OUT[3:0] pins R_L = ∞
OUT[3:0] pins R_L = ∞
4.75
5
5.5
1.8
VDD
V
1.8
VDD
4
mA
21
mW
I_PD
Supply Current, Power-Down
Mode
V_POR
Power-On Reset⁽⁶⁾
AC ELECTRICAL CHARACTERISTICS
50
µA
1.9
2.7
V
t_TRACK
t_HOLD
t_s
ADC Track Time
ADC Hold Time
DAC Settling Time⁽⁷⁾
Dictated by SPI bus activity
Dictated by SPI bus activity
25%FS to 75%FS code change,
R_L = 2K, C_L = 200 pF
t₈+9×t₁
µs
15×t₁
µs
20
µs
(6) During the power up the supply rail must ramp up beyond V_POR MIN for the device to acquire default state. After the supply rail has
reached the nominal level, the rail can drop as low as V_POR MAX for the current state to be maintained.
(7) Device Specification is guaranteed by characterization and is not tested in production.
8
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