DS90UB947-Q1 Datasheet, PDF (8/81 Pages) Texas Instruments – 1080p OpenLDI to FPD-Link III Serializer

DS90UB947-Q1
SNLS454 – NOVEMBER 2014
www.ti.com
7.6 AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
GPIO FREQUENCY⁽¹⁾
TEST CONDITIONS
PIN/FREQ.
MIN
R_b,FC
Forward Channel GPIO Single-Lane, CLK = 25MHz -
Frequency
96MHz
GPIO[3:0],
D_GPIO[3:0]
Dual-Lane, CLK/2 = 25MHz -
85MHz
t_GPIO,FC
GPIO Pulse Width,
Forward Channel
Single-Lane, CLK = 25MHz -
96MHz
GPIO[3:0],
D_GPIO[3:0]
>2 / CLK
Dual-Lane, CLK/2 = 25MHz -
85MHz
>2 / (CLK/2)
OpenLDI INPUTS
I_TJIT ⁽²⁾
Input Total Jitter
Tolerance
CLK±,
0.2
D[7:0]±
FPD-LINK III OUTPUT
t_LHT
Low Voltage Differential
Low-to-High Transition
Time
t_HLT
Low Voltage Differential
High-to-Low Transition
Time
t_XZD
Output Active to OFF
Delay
PDB = L
t_PLD
Lock Time (OpenLDI Rx)
t_SD
Delay — Latency
Random Pattern
t_DJIT
Output Total
Jitter(Figure 6 )
CLK±
Single-Lane:
High pass
filter CLK/20
Dual-lane:
High pass
filter CLK/40
λ_STXBW
Jitter Transfer Function
(-3dB Bandwidth)
δ_STX
Jitter Transfer Function
Peaking
TYP
MAX
UNIT
0.25 * CLK
0.125 * CLK
MHz
s
UI_OLDI ⁽³⁾
80
ps
80
ps
100
ns
5
10 ms
294
T ⁽⁴⁾
0.3
UI_FPD3 ⁽⁵⁾
1
MHz
0.1
dB
(1) Back channel rates are available on the companion deserializer datasheet.
(2) Includes data to clock skew, pulse position variation.
(3) One bit period of the OpenLDI input.
(4) Video pixel clock period when device in dual pixel OpenLDI input and dual FPD-Link III output modes.
(5) One bit period of the serializer output.
8
Submit Documentation Feedback
Product Folder Links: DS90UB947-Q1
Copyright © 2014, Texas Instruments Incorporated