DS90CF383B_15 Datasheet, PDF (8/18 Pages) Texas Instruments – +3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz

DS90CF383B
SNLS178E – JULY 2004 – REVISED APRIL 2013
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Pin Name
TxIN
TxOUT+
TxOUT−
FPSHIFT IN
TxCLK OUT+
TxCLK OUT−
PWR DOWN
V_CC
GND
PLL V_CC
PLL GND
LVDS V_CC
LVDS GND
DS90CF383B PIN DESCRIPTIONS — FPD LINK TRANSMITTER
I/O No.
Description
I
28 TTL level input. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines—FPLINE, FPFRAME and
DRDY (also referred to as HSYNC, VSYNC, Data Enable).
O
4 Positive LVDS differential data output.
O
4 Negative LVDS differential data output.
I
1 TTL Ievel clock input. The falling edge acts as data strobe. Pin name TxCLK IN.
O
1 Positive LVDS differential clock output.
O
1 Negative LVDS differential clock output.
I
1 TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at power down.
See Applications Information.
I
4 Power supply pins for TTL inputs.
I
5 Ground pins for TTL inputs.
I
1 Power supply pin for PLL.
I
2 Ground pins for PLL.
I
1 Power supply pin for LVDS outputs.
I
3 Ground pins for LVDS outputs.
8
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