DS90CF383B_15 Datasheet, PDF (4/18 Pages) Texas Instruments – +3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz

DS90CF383B
SNLS178E – JULY 2004 – REVISED APRIL 2013
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
Min
LLHT
LVDS Low-to-High Transition Time (Figure 4 )
LHLT
TPPos0
TPPos1
LVDS High-to-Low Transition Time (Figure 4 )
Transmitter Output Pulse Position for Bit 0 (Figure 11 )⁽¹⁾
Transmitter Output Pulse Position for Bit 1
f = 65
MHz
−0.20
2.00
TPPos2 Transmitter Output Pulse Position for Bit 2
4.20
TPPos3 Transmitter Output Pulse Position for Bit 3
6.39
TPPos4 Transmitter Output Pulse Position for Bit 4
8.59
TPPos5 Transmitter Output Pulse Position for Bit 5
10.70
TPPos6
TPPos0
TPPos1
Transmitter Output Pulse Position for Bit 6
Transmitter Output Pulse Position for Bit 0 (Figure 11 )⁽¹⁾
Transmitter Output Pulse Position for Bit 1
f = 40
MHz
12.99
−0.25
3.32
TPPos2 Transmitter Output Pulse Position for Bit 2
6.89
TPPos3 Transmitter Output Pulse Position for Bit 3
10.46
TPPos4 Transmitter Output Pulse Position for Bit 4
14.04
TPPos5 Transmitter Output Pulse Position for Bit 5
17.61
TPPos6
TPPos0
TPPos1
Transmitter Output Pulse Position for Bit 6
Transmitter Output Pulse Position for Bit 0 (Figure 11 )⁽¹⁾
Transmitter Output Pulse Position for Bit 1
f = 25
MHz
21.18
−0.45
5.26
TPPos2 Transmitter Output Pulse Position for Bit 2
10.98
TPPos3 Transmitter Output Pulse Position for Bit 3
16.69
TPPos4 Transmitter Output Pulse Position for Bit 4
22.41
TPPos5 Transmitter Output Pulse Position for Bit 5
28.12
TPPos6 Transmitter Output Pulse Position for Bit 6
33.84
TSTC TxIN Setup to TxCLK IN (Figure 6 )
2.5
THTC TxIN Hold to TxCLK IN (Figure 6 )
0.5
TCCD
SSCG
TxCLK IN to TxCLK OUT Delay (Figure 7 ) 50% duty cycle input clock is
assumed, T_A = −10°C, and 65MHz for " Min ", T_A = 70°C, and 25MHz for
" Max ", V_CC = 3.6V
Spread Spectrum Clock support; Modulation frequency with a linear
profile ⁽²⁾
f = 25
MHz
3.011
f = 40
MHz
f = 65
MHz
TPLLS Transmitter Phase Lock Loop Set (Figure 8 )
TPDD Transmitter Power Down Delay (Figure 10 )
Typ
0.75
0.75
0
2.20
4.40
6.59
8.79
10.99
13.19
0
3.57
7.14
10.71
14.29
17.86
21.43
0
5.71
11.43
17.14
22.86
28.57
34.29
100KHz ±
2.5%/−5%
100KHz ±
2.5%/−5%
100KHz ±
2.5%/−5%
www.ti.com
Max
1.4
1.4
+0.20
2.40
4.60
6.79
8.99
11.19
13.39
+0.25
3.82
7.39
10.96
14.54
18.11
21.68
+0.45
6.16
11.88
17.59
23.31
29.02
34.74
6.062
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
ms
100
ns
(1) The Minimum and Maximum Limits are based on statistical analysis of the device performance over process, voltage, and temperature
ranges. This parameter is functionality tested only on Automatic Test Equipment (ATE).
(2) Care must be taken to ensure TSTC and THTC are met so input data are sampling correctly. This SSCG parameter only shows the
performance of tracking Spread Spectrum Clock applied to TxCLK IN pin, and reflects the result on TxCLKOUT+ and TxCLK− pins.
4
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