DRV3204E-Q1 Datasheet, PDF (8/39 Pages) Texas Instruments – Three-Phase Brushless Motor Driver

DRV3204E-Q1
SLVSCB5A – OCTOBER 2013 – REVISED JANUARY 2013
www.ti.com
SERIAL PORT I/F
Description:
The device configuration is set and the diagnostic information read-out ocurrs through SPI. SPI operates in slave
mode. SPI uses four signals according as shown in the timing diagram of Figure 5.
Status
Enable
CS
SPI Control Logic and
8-Bit Shift Register
8-Bit Shift Register
DOUT
DIN
SCK
System Clock
Address Write Data
Read Data
Register Map
Figure 4. Block Diagram of SPI
CS - Chip Select
The MCU uses CS to select the IC. CS is normally high, and communication is possible only when CS is forced
low. When CS falls, communication between this IC and the MCU starts. The transmitted data are latched and
the DOUT output pin comes out of high impedance. When CS rises, communication stops. The DOUT output pin
goes into high impedance. The next falling edge starts another communication. There is a minimum waiting time
between two communications (t_wait). The pin has an internal pullup.
SCK - Synchronization Serial Clock
The MCU uses SCK to synchronize communication. SCK is normally low, and the valid clock-pulse number is 16.
At each falling edge, the MCU writes a new bit on the DIN input, and the IC writes a new bit on the DOUT output
pin. At each rising edge, the IC reads the new bit on DIN, and the MCU reads the new bit on DOUT. The
maximum clock frequency is 4 MHz. The pin has an internal pulldown.
DIN - Serial Input Data
DIN receives 16-bit data. The order of received bits is from the MSB (first) to the LSB (last). The pin has an
internal pulldown. Update of the internal register with the received bits occurs only if the number of clock pulses
is 16 while CS is low.
DOUT - Serial Output Data
DOUT transmits 16-bit data. DOUT is a three-state output, and is in the high-impedance state when CS is high.
The order of serial data-bit transmission is from the MSB (first) to the LSB (last).
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