DLP650NE Datasheet, PDF (8/44 Pages) Texas Instruments – 0.65 1080p S600 DMD

DLP650NE
DLPS097 – AUGUST 2017
www.ti.com
NAME ⁽²⁾
VBIAS
PIN
NO.
A6, A7, A8, AA6, AA7, AA8
Power Pin Functions
TYPE (I/O/P) ⁽¹⁾
SIGNAL
Analog
A3, A4, A25
Analog
VOFFSET
B26, L26, M26
Analog
N26, Z26, AA3, AA4
Analog
VRESET
G1, H1, J1, R1, T1, U1
VCC
A9, B3, B5, B12, C1, C6, C10,
D4, D6, D8, E1, E2, E10, E15,
E16, E17, F3, H2, K1, K3, M4,
P1, P3, T2, V3, W1, W2, W6,
W9, W10, W15, W16, W17, X3,
X6, Y1, Y8, Y13, Z1, Z3, Z12,
AA2, AA9, AA10
A16, A17, A18, A20, A21, A23,
P
VCCI
AA16, AA17, AA18, AA20, AA21,
AA23
A5, A10, A11, A19, A22, A24,
B2, B4, B9, B13, B17, B20, B21,
B24, C7, C15, C18, C21, C22,
C26, D1, D3, D7, D10, D12,
D14, D15, D16, D17, D18, D19,
D20, D21, D22, D23, D26, E6,
E8, E18, E19, E20, E21, E22,
E26, F1, F2, F4, F23, F26, G23,
G26, H3, H26, J26, K2, K4, K26,
VSS
L1, M1, M2, M3, M23, M24,
M25, N1, P2, P4, P26, R26, T3,
T26, U23, U26, V1, V2, V4, V23,
V26, W8, W18, W19, W20, W21,
W22, W26, X1, X2, X7, X10,
X12, X14, X15, X16, X17, X18,
X19, X20, X21, X22, X23, X26,
Y6, Y15, Y18, Y21, Y22, Y26,
Z2, Z4, Z9, Z13, Z17, Z20, Z21,
Z24, AA5, AA11, AA19, AA22,
AA24
Analog
Analog
Analog
Analog
DESCRIPTION
Supply voltage for positive Bias
level of Micromirror reset signal
Supply voltage for HVCMOS
logic
Supply voltage for stepped high
voltage at Micromirror address
electrodes
Supply voltage for positive Offest
level of Micromirror reset signal.
Supply voltage for negative
Reset level of Micromirror reset
signal.
Supply voltage for LVCMOS core
logic. Supply voltage for normal
high level at Micromirror address
electrodes. Supply voltage for
positive Offset level of
Micromirror reset signal during
Power Down sequence.
Supply voltage for LVDS
receivers.
Device ground. Common return
for all power.
(1) P = Power
(2) The following power supplies are required to operate the DMD: VCC, VCCI, VOFFSET, VBIAS, and VRESET. VSS must also be
connected.
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