DLP650NE Datasheet, PDF (15/44 Pages) Texas Instruments – 0.65 1080p S600 DMD

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t_c
f_clock = 1 / t_c
SCPCLK
50%
50%
t_{SCP_SKEW}
SCPDI
50%
t_{SCP_DELAY}
SCPD0
50%
Not to scale.
Refer to SCP Interface section of the Recommended Operating Conditions table.
Figure 2. SCP Timing Parameters
DLP650NE
DLPS097 – AUGUST 2017
(V_IP + V_IN) / 2
DCLK_P , SCTRL_P , D_P(0:?)
V_ID
V_IP
DCLK_N , SCTRL_N , D_N(0:?)
LVDS
Receiver
V_CM
V_IN
Refer to LVDS Interface section of the Recommended Operating Conditions table.
Refer to Pin Configuration and Functions for list of LVDS pins.
Figure 3. LVDS Voltage Definitions (References)
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