ADS8509-HT Datasheet, PDF (8/29 Pages) Texas Instruments – 16-BIT 250-KSPS SERIAL CMOS SAMPLING ANALOG-TO-DIGITAL CONVERTER

ADS8509-HT
SLAS737A – DECEMBER 2012 – REVISED DECEMBER 2013
www.ti.com
TERMINAL
NAME
NO.
AGND1
2
AGND2
9
BUSY
25
CAP
6
CS
24
DATA
17
DATACLK
16
DGND
14
EXT/INT
13
NC
PWRD
R/C
5, 8, 10,
11, 18,
20, 22,
23
26
21
REF
7
R1_IN
1
R2_IN
3
R3_IN
4
SB/BTC
12
SYNC
15
TAG
19
V_ANA
27
V_DIG
28
Terminal Functions
DESCRIPTION
I/O
– Analog ground. Used internally as ground reference point. Minimal current flow.
– Analog ground
O Busy output. Falls when a conversion is started and remains low until the conversion is completed and the
data is latched into the output shift register.
– Reference buffer capacitor. 2.2-μF Tantalum to ground.
– Chip select. Internally ORed with R/C.
O Serial data output. Data is synchronized to DATACLK with the format determined by the level of SB/BTC.
In the external clock mode, after 16 bits of data, the ADS8509 outputs the level input on TAG as long as
CS is low and R/C is high (see Figure 8 and Figure 9). If EXT/INT is low, data is valid on both the rising
and falling edges of DATACLK, and between conversions DATA stays at the level of the TAG input when
the conversion was started.
I/O Either an input or an output depending on the EXT/INT level. Output data is synchronized to this clock. If
EXT/INT is low, DATACLK transmits 16 pulses after each conversion and then remains low between
conversions.
– Digital ground
– Selects external or internal clock for transmitting data. If high, data is output synchronized to the clock
input on DATACLK. If low, a convert command initiates the transmission of the data from the previous
conversion, along with 16-clock pulses output on DATACLK.
– No connect
I Power down input. If high, conversions are inhibited and power consumption is significantly reduced.
Results from the previous conversion are maintained in the output shift register.
I Read/convert input. With CS low, a falling edge on R/C puts the internal sample-and-hold into the hold
state and starts a conversion. When EXT/INT is low, this also initiates the transmission of the data results
from the previous conversion. If EXT/INT is high, a rising edge on R/C with CS low or a falling edge on
CS with R/C high transmits a pulse on SYNC and initiates the transmission of data from the previous
conversion.
I/O Reference input/output. Outputs internal 2.5-V reference. Can also be driven by external system
reference. In both cases, bypass to ground with a 2.2-μF tantalum capacitor.
I Analog input. See Table 2 for input range connections.
I Analog input. See Table 2 for input range connections.
I Analog input. See Table 2 for input range connections.
I Select straight binary or binary 2's complement data output format. If high, data is output in a straight
binary format. If low, data is output in a binary 2's complement format.
O Sync output. This pin is used to supply a data synchronization pulse when the EXT level is high and at
least one external clock pulse has occurred when not in the read mode. See the external clock modes
desciptions.
I Tag input for use in the external clock mode. If EXT is high, digital data input from TAG is output on DATA
with a delay that is dependent on the external clock mode. See Figure 8 and Figure 9.
I Analog supply input. Nominally +5 V. Connect directly to pin 20 and decouple to ground with 0.1-μF
ceramic and 10-μF tantalum capacitors.
I Digital supply input. Nominally +5 V. Connect directly to pin 19. Must be ≤ V_ANA.
8
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