ADS8509-HT Datasheet, PDF (18/29 Pages) Texas Instruments – 16-BIT 250-KSPS SERIAL CMOS SAMPLING ANALOG-TO-DIGITAL CONVERTER

ADS8509-HT
SLAS737A – DECEMBER 2012 – REVISED DECEMBER 2013
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TYPICAL CHARACTERISTICS (continued)
FFT (20-kHz Input)
8192 Points,
f_s = 250 KSPS,
f_i = 20 kHz, 0 dB
SINAD = 86.0 dB,
THD = −98.7 dB
25
50
75
100
125
f − Frequency − kHz
Figure 26.
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BASIC OPERATION
Two signals control conversion in the ADS8509: CS and R/C. These two signals are internally ORed together. To
start a conversion the chip must be selected, CS low, and the conversion signal must be active, R/C low. Either
signal can be brought low first. Conversion starts on the falling edge of the second signal. BUSY goes low when
conversion starts and returns high after the data from that conversion is shifted into the internal storage register.
Sampling begins when BUSY goes high.
To reduce the number of control pins CS can be tied low permanently. The R/C pin now controls conversion and
data reading exclusively. In the external clock mode this means that the ADS8509 clocks out data whenever R/C
is brought high and the external clock is active. In the internal clock mode data is clocked out every convert cycle
regardless of the states of CS and R/C. The ADS8509 provides a TAG input for cascading multiple converters
together.
READING DATA
The conversion result is available as soon as BUSY returns to high, therefore data always represents the
conversion previously completed even when it is read during a conversion. The ADS8509 outputs serial data in
either straight binary or binary two’s compliment format. The SB/BTC pin controls the format. Data is shifted out
MSB first. The first conversion immediately following a power-up does not produce a valid conversion result.
Data can be clocked out with either the internally generated clock or with an external clock. The EXT/INT pin
controls this function. If an external clock is used, the TAG input can be used to daisy-chain multiple ADS8509
data pins together.
INTERNAL DATACLK
In internal clock mode data for the previous conversion is clocked out during each conversion period. The
internal data clock is synchronized to the internal conversion clock so that is does not interfere with the
conversion process.
The DATACLK pin becomes an output when EXT/INT is low. 16 Clock pulses are generated at the beginning of
each conversion after timing t₈ is satisfied, i.e. only the previous conversion result can be read during conversion.
DATACLK returns to low when it is inactive. The 16 bits of serial data are shifted out the DATA pin synchronous
to this clock with each bit available on a rising and then a falling edge. The DATA pin returns to the state of the
TAG pin input sensed at the start of transmission.
EXTERNAL DATACLK
The external clock mode offers several ways to retrieve conversion results. However, since the external clock
cannot be synchronized to the internal conversion clock care must be taken to avoid corrupting the data.
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