ADC12040_14 Datasheet, PDF (8/30 Pages) Texas Instruments – 12-Bit, 40 MSPS, 340mW A/D Converter with Internal Sample-and-Hold

ADC12040
SNAS135G – FEBRUARY 2001 – REVISED MARCH 2013
www.ti.com
AC Electrical Characteristics
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, V_A = V_D = +5V, V_DR =
+3.0V, PD = 0V, V_REF = +2.0V, f_CLK = 40 MHz, t_r = t_f = 3 ns, C_L = 20 pF/pin. Boldface limits apply for T_A = T_J = T_MIN to T_MAX:
all other limits T_A = T_J = 25°C ^(1)(2)(3)(4)
Symbol
Parameter
Conditions
Typical Limits
(5)
(5)
Units
(Limits)
f_CLK¹
f_CLK²
t_CH
t_CL
t_CONV
Maximum Clock Frequency
Minimum Clock Frequency
Clock High Time
Clock Low Time
Conversion Latency
t_OD
Data Output Delay after Rising CLK Edge
t_AD
Aperture Delay
t_AJ
Aperture Jitter
t_DIS
Data outputs into TRI-STATE Mode
t_EN
Data Outputs Active after TRI-STATE
t_PD
Power Down Mode Exit Cycle
V_DR = 2.5V, −45°C < T_A < +85°C
V_DR = 2.5V, T_A = +25°C
V_DR = 3.0V, −45°C < T_A < +85°C
V_DR = 3.0V, T_A = +25°C
50
40
MHz (min)
100
kHz
11.25
ns (min)
11.25
ns (min)
6
Clock Cycles
16.3
ns (max)
12
15.9
ns (max)
15.7
ns (max)
11
14.9
ns (max)
1.2
ns
1.2
ps rms
4
ns
4
ns
20
t_CLK
(1) The inputs are protected as shown below. Input voltage magnitudes above V_A or below GND will not damage this device, provided
current is limited per ⁽⁾. However, errors in the A/D conversion can occur if the input goes above V_A or below GND by more than 100
mV. As an example, if V_A is 4.75V, the full-scale input voltage must be ≤4.85V to ensure accurate conversions. See Figure 1
(2) To ensure accuracy, it is required that |V_A–V_D| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.
(3) With the test condition for V_REF = +2.0V (4V_P-P differential input), the 12-bit LSB is 977 µV.
(4) Timing specifications are tested at TTL logic levels, V_IL = 0.4V for a falling edge and V_IH = 2.4V for a rising edge.
(5) Typical figures are at T_A = T_J = 25°C, and represent most likely parametric norms. Test limits are specified to TI's AOQL (Average
Outgoing Quality Level).
Figure 1.
Specification Definitions
APERTURE DELAY is the time after the rising edge of the clock to when the input signal is acquired or held for
conversion.
APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample.
Aperture jitter manifests itself as noise in the output.
CLOCK DUTY CYCLE is the ratio of the time during one cycle that a repetitive digital waveform is high to the
total time of one period. The specification here refers to the ADC clock input signal.
COMMON MODE VOLTAGE (V_CM) is the d.c. potential present at both signal inputs to the ADC.
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