LM3S6G65 Datasheet, PDF (795/1044 Pages) Texas Instruments – Stellaris® LM3S6G65 Microcontroller

OBSOLETE: TI has discontinued production of this device.
Stellaris^® LM3S6G65 Microcontroller
Register 16: Ethernet PHY MDIX (MDIX), offset 0x044
This register enables the transmit and receive lines to be reversed in order to implement the
MDI/MDI-X functionality. Software can implement the MDI/MDI-X configuration by using any available
timer resource such as SysTick (see “System Timer (SysTick)” on page 97 for more information)
to implement this functionality. Once the Ethernet Controller has been configured and enabled,
software should check to see if the LINK bit in the MR1 register has been set within approximately
1 s; if not, set the EN bit of the MDIX register to switch the reverse the transmit and receive lines to
the PHY layer. Software should check the LINK bit again after approximately another 1 s and if no
link has been established, the EN bit should be cleared. Software must continue to change the
termination back and forth by setting and clearing the EN bit every 1 s until a link is established.
Ethernet PHY MDIX (MDIX)
Base 0x4004.8000
Offset 0x044
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
EN
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:1
0
Name
reserved
EN
Type
Reset Description
RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W
0
MDI/MDI-X Enable
Value Description
1 The transmit and receive signals are switched such that data
is received on the transmit signals TXOP and TXON; data is
transmitted on the receive signals RXIP and RXIN
0 No effect.
16.7
MII Management Register Descriptions
The IEEE 802.3 standard specifies a register set for controlling and gathering status from the PHY
layer. The registers are collectively known as the MII Management registers. The Ethernet MAC
Management Control (MACMCTL) register is used to access the MII Management registers, see
page 786. All addresses given are absolute. Addresses not listed are reserved; these addresses
should not be written to and any data read should be ignored. Also see “Ethernet MAC Register
Descriptions” on page 770.
July 24, 2012
795
Texas Instruments-Production Data