LM3S6G65 Datasheet, PDF (430/1044 Pages) Texas Instruments – Stellaris® LM3S6G65 Microcontroller

OBSOLETE: TI has discontinued production of this device.
General-Purpose Input/Outputs (GPIOs)
Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420
The GPIOAFSEL register is the mode control select register. If a bit is clear, the pin is used as a
GPIO and is controlled by the GPIO registers. Setting a bit in this register configures the
corresponding GPIO line to be controlled by an associated peripheral. Several possible peripheral
functions are multiplexed on each GPIO. The GPIO Port Control (GPIOPCTL) register is used to
select one of the possible functions. Table 21-5 on page 948 details which functions are muxed on
each GPIO pin. The reset value for this register is 0x0000.0000 for GPIO ports that are not listed
in the table below.
Important: All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0,
GPIODEN=0, GPIOPDR=0, GPIOPUR=0, and GPIOPCTL=0, with the exception of the
pins shown in the table below. A Power-On-Reset (POR) or asserting RST puts the pins
back to their default state.
Table 9-8. GPIO Pins With Non-Zero Reset Values
GPIO Pins
PA[1:0]
PA[5:2]
PB[3:2]
PC[3:0]
Default State
UART0
SSI0
I²C0
JTAG/SWD
GPIOAFSEL GPIODEN GPIOPDR GPIOPUR
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
GPIOPCTL
0x1
0x2
0x3
0x1
Caution – It is possible to create a software sequence that prevents the debugger from connecting to
the Stellaris microcontroller. If the program code loaded into flash immediately changes the JTAG pins
to their GPIO functionality, the debugger may not have enough time to connect and halt the controller
before the JTAG pin functionality switches. As a result, the debugger may be locked out of the part.
This issue can be avoided with a software routine that restores JTAG functionality based on an external
or software trigger.
The GPIO commit control registers provide a layer of protection against accidental programming of
critical hardware peripherals. Protection is provided for the NMI pin (PB7) and the four JTAG/SWD
pins (PC[3:0]). Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL)
register (see page 430), GPIO Pull Up Select (GPIOPUR) register (see page 436), GPIO Pull-Down
Select (GPIOPDR) register (see page 438), and GPIO Digital Enable (GPIODEN) register (see
page 441) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see page 443)
has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see page 444)
have been set.
When using the I²C module, in addition to setting the GPIOAFSEL register bits for the I²C clock
and data pins, the data pins should be set to open drain using the GPIO Open Drain Select
(GPIOODR) register (see examples in “Initialization and Configuration” on page 416).
430
July 24, 2012
Texas Instruments-Production Data