LM3S1621_15 Datasheet, PDF (79/948 Pages) Texas Instruments – Stellaris LM3S1621 Microcontroller

Stellaris^® LM3S1621 Microcontroller
2.3.5
2.3.6
Exceptions and Interrupts
The Cortex-M3 processor supports interrupts and system exceptions. The processor and the Nested
Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. An exception changes the
normal flow of software control. The processor uses Handler mode to handle all exceptions except
for reset. See “Exception Entry and Return” on page 93 for more information.
The NVIC registers control interrupt handling. See “Nested Vectored Interrupt Controller
(NVIC)” on page 103 for more information.
Data Types
The Cortex-M3 supports 32-bit words, 16-bit halfwords, and 8-bit bytes. The processor also supports
64-bit data transfer instructions. All instruction and data memory accesses are little endian. See
“Memory Regions, Types and Attributes” on page 81 for more information.
2.4 Memory Model
This section describes the processor memory map, the behavior of memory accesses, and the
bit-banding features. The processor has a fixed memory map that provides up to 4 GB of addressable
memory.
The memory map for the LM3S1621 controller is provided in Table 2-4 on page 79. In this manual,
register addresses are given as a hexadecimal increment, relative to the module’s base address
as shown in the memory map.
The regions for SRAM and peripherals include bit-band regions. Bit-banding provides atomic
operations to bit data (see “Bit-Banding” on page 84).
The processor reserves regions of the Private peripheral bus (PPB) address range for core peripheral
registers (see “Cortex-M3 Peripherals” on page 102).
Note: Within the memory map, all reserved space returns a bus fault when read or written.
Table 2-4. Memory Map
Start
End
Memory
0x0000.0000
0x0002.0000
0x0100.0000
0x2000.0000
0x2000.8000
0x2200.0000
0x0001.FFFF
0x00FF.FFFF
0x1FFF.FFFF
0x2000.7FFF
0x21FF.FFFF
0x220F.FFFF
0x2210.0000
FiRM Peripherals
0x4000.0000
0x4000.1000
0x4000.2000
0x4000.4000
0x4000.5000
0x4000.6000
0x3FFF.FFFF
0x4000.0FFF
0x4000.1FFF
0x4000.3FFF
0x4000.4FFF
0x4000.5FFF
0x4000.6FFF
Description
On-chip Flash
Reserved
Reserved for ROM
Bit-banded on-chip SRAM
Reserved
Bit-band alias of bit-banded on-chip SRAM starting at
0x2000.0000
Reserved
Watchdog timer 0
Watchdog timer 1
Reserved
GPIO Port A
GPIO Port B
GPIO Port C
For details,
see page ...
310
-
302
302
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302
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574
574
-
408
408
408
July 03, 2014
79
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