LM3S1621_15 Datasheet, PDF (229/948 Pages) Texas Instruments – Stellaris LM3S1621 Microcontroller

Stellaris^® LM3S1621 Microcontroller
Register 17: Device Capabilities 1 (DC1), offset 0x010
This register is predefined by the part and can be used to verify features. If any bit is clear in this
register, the module is not present. The corresponding bit in the RCGC0, SCGC0, and DCGC0
registers cannot be set.
Device Capabilities 1 (DC1)
Base 0x400F.E000
Offset 0x010
Type RO, reset -
31
30
29
28
reserved
WDT1
Type RO
RO
RO
RO
Reset
0
0
0
1
15
14
13
12
MINSYSDIV
Type RO
RO
RO
RO
Reset
-
-
-
-
27
26
RO
RO
0
0
11
10
reserved
RO
RO
0
0
25
24
RO
RO
0
0
9
8
MAXADC0SPD
RO
RO
1
1
23
22
21
20
reserved
RO
RO
RO
RO
0
0
0
0
7
MPU
RO
1
6
5
4
HIB TEMPSNS PLL
RO
RO
RO
1
1
1
19
18
RO
0
3
WDT0
RO
1
RO
0
2
SWO
RO
1
17
RO
0
1
SWD
RO
1
16
ADC0
RO
1
0
JTAG
RO
1
Bit/Field
31:29
28
27:17
16
15:12
Name
reserved
WDT1
reserved
ADC0
MINSYSDIV
Type
RO
RO
RO
RO
RO
Reset
0
1
0
1
-
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Watchdog Timer 1 Present
When set, indicates that watchdog timer 1 is present.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
ADC Module 0 Present
When set, indicates that ADC module 0 is present
System Clock Divider
Minimum 4-bit divider value for system clock. The reset value is
hardware-dependent. See the RCC register for how to change the
system clock divisor using the SYSDIV bit.
Value Description
0x1 Specifies an 80-MHz CPU clock with a PLL divider of 2.5.
0x2 Specifies a 66.67-MHz CPU clock with a PLL divider of 3.
0x3 Specifies a 50-MHz CPU clock with a PLL divider of 4.
0x7 Specifies a 25-MHz clock with a PLL divider of 8.
0x9 Specifies a 20-MHz clock with a PLL divider of 10.
11:10
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
July 03, 2014
229
Texas Instruments-Production Data