ADC12D800RFIUT Datasheet, PDF (79/84 Pages) Texas Instruments – 12-Bit, 1.6/1.0 GSPS RF Sampling ADC

ADC12D500RF, ADC12D800RF
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Table 6-30. AutoSync⁽¹⁾
SNAS502E – JULY 2011 – REVISED MARCH 2013
Addr: Eh (1110b)
POR state: 0003h
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
DRC(8:0)
DCK Res
SP(1:0)
ES DOC DR
POR 0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
(1) This feature functionality is not tested in production test; performance is tested in the specified/default mode only.
Bits 15:7
DRC(8:0): Delay Reference Clock (8:0). These bits may be used to increase the delay on the input reference clock when
synchronizing multiple ADCs. The delay may be set from a minimum of 0s (0d) to a maximum of 1200 ps (319d). The delay
remains the maximum of 1200 ps for any codes above or equal to 319d. See SYNCHRONIZING MULTIPLE
ADC12D800/500RFS IN A SYSTEM for more information.
Bit 6
DCK: DESCLKIQ Mode. Set this bit to 1b to enable Dual-Edge Sampling, in which the Sampling Clock samples the I- and Q-
channels 180º out of phase with respect to one another, i.e. the DESCLKIQ Mode. To select the DESCLKIQ Mode, Addr: 0h,
Bits <7:5> must also be set to 000b. See Input Control and Adjust for more information.⁽¹⁾
Bit 5
Reserved. Must be set as shown.
Bits 4:3
SP(1:0): Select Phase. These bits select the phase of the reference clock which is latched. The codes correspond to the
following phase shift:
00 = 0°
01 = 90°
10 = 180°
11 = 270°
Bit 2
ES: Enable Slave. Set this bit to 1b to enable the Slave Mode of operation. In this mode, the internal divided clocks are
synchronized with the reference clock coming from the master ADC. The master clock is applied on the input pins RCLK. If this
bit is set to 0b, then the device is in Master Mode.
Bit 1
DOC: Disable Output reference Clocks. Setting this bit to 0b sends a CLK/4 signal on RCOut1 and RCOut2. The default
setting of 1b disables these output drivers. This bit functions as described, regardless of whether the device is operating in
Master or Slave Mode, as determined by ES (Bit 2).
Bit 0
DR: Disable Reset. The default setting of 1b leaves the DCLK_RST functionality disabled. Set this bit to 0b to enable
DCLK_RST functionality.
(1) This feature functionality is not tested in production test; performance is tested in the specified/default mode only.
Table 6-31. Reserved
Addr: Fh (1111b)
POR state: 001Dh
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Res
POR 0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
Bits 15:0 Reserved. This address is read only.
Copyright © 2011–2013, Texas Instruments Incorporated
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Functional Description
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