LM3S9L97_15 Datasheet, PDF (788/1337 Pages) Texas Instruments – Stellaris LM3S9L97 Microcontroller

Inter-Integrated Circuit Sound (I²S) Interface
Table 16-8. I²S Receive FIFO Interface
RM bit in
I2RXCFG
0
1
1
0
CSS bit in Read Mode
I2SRXFIFOCFG
don't care Stereo
0
Compact Stereo - 16 bit
1
don't care
Compact Stereo - 8 bit
Mono (FMM bit in the
I2SRXFIFOCFG register must
be set.)
Sample Width
8-32 bits
8-16 bits
8 bits
8-32 bits
Samples per
FIFO Read
Data Alignment
1
MSB
2
MSB Right [31:15], Left
[15:0]
2
Right [15:8] Left[7:0]
1
MSB
The number of samples in the receive FIFO can be read using the I²S Receive FIFO Level
(I2SRXLEV) register. The value ranges from 0 to 16. Stereo and compact stereo sample pairs are
counted as two. The mono samples also increment the count by two, therefore four Mono samples
will have a count of eight.
16.3.2.3
Clock Control
The receiver MCLK and SCLK can be independently programmed to be the master or slave. The
receiver is programmed to be the master or slave of the SCLK using the MSL bit in the I2SRXCFG
register. When the receiver is the master, the I2S0RXSCK frequency is the specified I2S0RXMCLK
divided by four. The I2S0RXSCK may be inverted using the SCP bit in the I2SRXCFG register.
The receiver can also be the master or slave of the MCLK. When the receiver is the master, the
PLL must be active and a fractional clock divider must be programmed. See page 245 for the setup
for the master I2S0RXMCLK source. An external transmit I2S0RXMCLK does not require the use of
the PLL and is selected using the RXSLV bit in the I2SCFG register.
Refer to “Clock Control” on page 784 for combinations of the RXINT and RXFRAC bits in the I²S
MCLK Configuration (I2SMCLKCFG) register that provide MCLK frequencies within acceptable
error limits. In the table, Fs is the sampling frequency in kHz and possible crystal frequencies are
shown in MHz across the top row of the table. The words "not supported" in the table mean that it
is not possible to obtain the specified sampling frequencies with the specified crystal frequency
within the error tolerance of 0.3%.
16.3.2.4
Interrupt Control
A single interrupt is asserted to the CPU whenever any of the transmit or receive sources is asserted.
The receive module has two interrupt sources: the FIFO service request and read error. The interrupts
may be masked using the RXSRIM and RXREIM bits in the I2SIM register. The status of the interrupt
source is indicated by the I2SRIS register. The status of enabled interrupts is indicated by the I2SMIS
register. The FIFO service request interrupt has a second level of masking using the FFM bit in the
I²S Receive Interrupt Status and Mask (I2SRXISM) register. The sources may be masked using
the I2SIM register.
The FIFO service request interrupt is asserted when the FIFO level (indicated by the LEVEL field
in the I²S Receive FIFO Level (I2SRXLEV) register) is above the FIFO limit (programmed using
the I²S Receive FIFO Limit (I2SRXLIMIT) register) and both the RXSRIM and FFM bits are set. An
error occurs when reading an empty FIFO or if a stereo sample pair is not read left then right. To
clear an interrupt, write a 1 to the appropriate bit in the I2SIC register. If software attempts to read
an empty FIFO or if a stereo sample pair is not read left then right, a Receive FIFO Read error
occurs (indicated by the RXRERIS bit in the I2SRIS register). The RXRERIS bit in the I2SRIS register
and the RXREMIS bit in the I2SMIS register are cleared by setting the RXREIC bit in the I2SIC
register.
788
July 03, 2014
Texas Instruments-Production Data