LM3S9L97_15 Datasheet, PDF (636/1337 Pages) Texas Instruments – Stellaris LM3S9L97 Microcontroller

Universal Asynchronous Receivers/Transmitters (UARTs)
13.1
– Transmit single request asserted when there is space in the FIFO; burst request asserted at
programmed FIFO level
Block Diagram
Figure 13-1. UART Module Block Diagram
System Clock
DMA Request
Interrupt
Identification
Registers
UARTPCellID0
UARTPCellID1
UARTPCellID2
UARTPCellID3
UARTPeriphID0
UARTPeriphID1
UARTPeriphID2
UARTPeriphID3
UARTPeriphID4
UARTPeriphID5
UARTPeriphID6
UARTPeriphID7
DMA Control
UARTDMACTL
Interrupt Control
UARTIFLS
UARTIM
UARTMIS
UARTRIS
UARTICR
UARTDR
Control/Status
UARTRSR/ECR
UARTFR
UARTLCRH
UARTCTL
UARTILPR
UARTLCTL
UARTLSS
UARTLTIM
TxFIFO
16 x 8
.
.
.
Baud Rate
Generator
UARTIBRD
UARTFBRD
RxFIFO
16 x 8
.
.
.
Transmitter
(with SIR
Transmit
Encoder)
Receiver
(with SIR
Receive
Decoder)
UnTx
UnRx
13.2
Signal Description
The following table lists the external signals of the UART module and describes the function of each.
The UART signals are alternate functions for some GPIO signals and default to be GPIO signals at
reset, with the exception of the U0Rx and U0Tx pins which default to the UART function. The column
in the table below titled "Pin Mux/Pin Assignment" lists the possible GPIO pin placements for these
UART signals. The AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL) register
(page 451) should be set to choose the UART function. The number in parentheses is the encoding
that must be programmed into the PMCn field in the GPIO Port Control (GPIOPCTL) register
(page 469) to assign the UART signal to the specified GPIO port pin. For more information on
configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 428.
636
July 03, 2014
Texas Instruments-Production Data