LM3S310 Datasheet, PDF (78/506 Pages) List of Unclassifed Manufacturers – Microcontroller

The Cortex-M3 Processor
2.7.2.1
2.7.2.2
2.8
Wake Up from WFI or Sleep-on-Exit
Normally, the processor wakes up only when the NVIC detects an exception with sufficient priority
to cause exception entry. Some embedded systems might have to execute system restore tasks
after the processor wakes up and before executing an interrupt handler. Entry to the interrupt handler
can be delayed by setting the PRIMASK bit and clearing the FAULTMASK bit. If an interrupt arrives
that is enabled and has a higher priority than current exception priority, the processor wakes up but
does not execute the interrupt handler until the processor clears PRIMASK. For more information
about PRIMASK and FAULTMASK, see page 55 and page 56.
Wake Up from WFE
The processor wakes up if it detects an exception with sufficient priority to cause exception entry.
In addition, if the SEVONPEND bit in the SYSCTRL register is set, any new pending interrupt triggers
an event and wakes up the processor, even if the interrupt is disabled or has insufficient priority to
cause exception entry. For more information about SYSCTRL, see page 111.
Instruction Set Summary
The processor implements a version of the Thumb instruction set. Table 2-13 on page 78 lists the
supported instructions.
Note: In Table 2-13 on page 78:
■ Angle brackets, <>, enclose alternative forms of the operand
■ Braces, {}, enclose optional operands
■ The Operands column is not exhaustive
■ Op2 is a flexible second operand that can be either a register or a constant
■ Most instructions can use an optional condition code suffix
For more information on the instructions and operands, see the instruction descriptions in
the Cortex™-M3/M4 Instruction Set Technical User's Manual.
Table 2-13. Cortex-M3 Instruction Summary
Mnemonic
ADC, ADCS
ADD, ADDS
ADD, ADDW
ADR
AND, ANDS
ASR, ASRS
B
BFC
BFI
BIC, BICS
BKPT
BL
BLX
BX
CBNZ
Operands
{Rd,} Rn, Op2
{Rd,} Rn, Op2
{Rd,} Rn , #imm12
Rd, label
{Rd,} Rn, Op2
Rd, Rm, <Rs|#n>
label
Rd, #lsb, #width
Rd, Rn, #lsb, #width
{Rd,} Rn, Op2
#imm
label
Rm
Rm
Rn, label
Brief Description
Add with carry
Add
Add
Load PC-relative address
Logical AND
Arithmetic shift right
Branch
Bit field clear
Bit field insert
Bit clear
Breakpoint
Branch with link
Branch indirect with link
Branch indirect
Compare and branch if non-zero
Flags
N,Z,C,V
N,Z,C,V
N,Z,C,V
-
N,Z,C
N,Z,C
-
-
-
N,Z,C
-
-
-
-
-
78
July 14, 2014
Texas Instruments-Production Data