LM3S310 Datasheet, PDF (102/506 Pages) List of Unclassifed Manufacturers – Microcontroller

Cortex-M3 Peripherals
Bit/Field
28:24
23:21
20:16
15:13
12:8
7:5
4:0
Name
reserved
INTC
reserved
INTB
reserved
INTA
reserved
Type
RO
R/W
RO
R/W
RO
R/W
RO
Reset
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Interrupt Priority for Interrupt [4n+2]
This field holds a priority value, 0-7, for the interrupt with the number
[4n+2], where n is the number of the Interrupt Priority register (n=0 for
PRI0, and so on). The lower the value, the greater the priority of the
corresponding interrupt.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Interrupt Priority for Interrupt [4n+1]
This field holds a priority value, 0-7, for the interrupt with the number
[4n+1], where n is the number of the Interrupt Priority register (n=0 for
PRI0, and so on). The lower the value, the greater the priority of the
corresponding interrupt.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Interrupt Priority for Interrupt [4n]
This field holds a priority value, 0-7, for the interrupt with the number
[4n], where n is the number of the Interrupt Priority register (n=0 for
PRI0, and so on). The lower the value, the greater the priority of the
corresponding interrupt.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
102
July 14, 2014
Texas Instruments-Production Data