VSP01M01 Datasheet, PDF (74/91 Pages) Texas Instruments – CCD Analog Front-End with Timing Generator and Vertical Driver for Digital Cameras

VSP01M01
VSP01M02
SBES016 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com
ADDRESS
SECTION DEC HEX BITS
—
Update
[2:1]
0—
[3]
[5:4]
Detailed Common Section
PARAMETER
PARAMETER # OF BITS
DESCRIPTION
—
—
—
AFE UP POL
TG update
—
2
AFE register update
signal and polarity
1
TG register update
timing
2
—
DESCRIPTION
VALUE
0 = Real time
1 = External trigger (R_LOAD pin or VD)
00b = R_LOAD input rising edge (default)
01b = R_LOAD input falling edge
10b = VD rising edge
11b = VD falling edge
0 = Real time
1 = VA internal instruction (R_UPDATE) (default)
Reserved
Default = 00b
UPDATE
METHOD
Real time
Detailed AFE Section
ADDRESS
SECTION DEC HEX BITS
[0]
[1]
Standby 1 1 [2]
[3]
[5:4]
[1:0]
Data out 2 2
[2]
[5:3]
S-DELAY 3
[1:0]
3
[5:2]
OB clamp 4
[4:0]
4
Hot-pixel
rejection
5
[5]
[4:0]
5
[5]
PARAMETER
PARAMETER # OF BITS
DESCRIPTION
DESCRIPTION
VALUE
UPDATE
METHOD
AFE standby
1
AFE standby
0 = AFE functions normally (default)
1 = AFE standby
8-bit DAC1
standby
8-bit DAC2
standby
Monitor pin
1
Independent 8-bit DAC1
standby
0 = Enabled
1
Independent 8-bit DAC2 ^{1 = Standby (default)}
standby
1
Monitor pin enable
0 = Disabled (default)
1 = Enabled
Real time,
VD, or
R_LOAD
(selected
by
000h[2:0])
—
2
—
Reserved
Default = 00b
Data out delay
OE
—
2
Data out delay
1
Data output enable
3
—
00b = 0 ns (default)
01b = 2 ns
10b = 4 ns
11b = 6 ns
0 = Enabled (default)
1 = Disabled (high impedance)
Reserved
Default = 000b
Real time,
VD, or
R_LOAD
(selected
by
000h[2:0])
←
2
Sampling delay for
SHP/SHD internal delay
circuit
00b = 0 ns (default)
01b = 2 ns
10b = 4 ns
11b = 6 ns
—
4
—
Reserved
Default = 0000b
Real time,
VD, or
R_LOAD
(selected
by
000h[2:0])
DATA
(DEC)
12-BIT
10-BIT
00000b
(0)
64
16
00001b
(1)
72
18
—
—
—
—
00110b
(6)
112
28
←
5
OB clamp level
00111b
(7)
01000b
(8)
01001b
(9)
—
—
01110b
(14)
01111b
(15)
—
—
120
128
136
—
176
184
—
30
32 (default)
34
—
44
46
—
Real time,
VD, or
R_LOAD
(selected
by
000h[2:0])
11110b
(30)
304
76
11111b
(31)
312
78
Step
—
8
2
—
1
—
Reserved
Default = 0
HOT PIX LEVEL
HOT PIX EN
5
Hot-pixel rejection level
R_L (LSB) = 16 × (code[4:0] + 1) (R_L is the
difference from OB level of 10-bit equivalent)
1
Hot-pixel rejection
enable/disable
0 = Disabled (default)
1 = Enabled
Real time,
VD, or
R_LOAD
(selected
by
000h[2:0])
74
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): VSP01M01 VSP01M02