VSP01M01 Datasheet, PDF (1/91 Pages) Texas Instruments – CCD Analog Front-End with Timing Generator and Vertical Driver for Digital Cameras

VSP01M01
VSP01M02
www.ti.com .................................................................................................................................................................................................. SBES016 – MARCH 2009
CCD Analog Front-End with Timing Generator and Vertical Driver for Digital Cameras
FEATURES
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• CCD Signal Processing:
– 36-MHz Correlated Double Sampling (CDS)
• 16-Bit Analog-to Digital Conversion:
– 36-MHz Conversion Rate
– No Missing Codes Ensured
• 80-dB Input-Referred SNR (at 12-dB Gain)
• Programmable Black Level Clamping
• Programmable Gain Amplifier (PGA):
– –9 dB to +44 dB
–3 dB to +18 dB by Analog Front Gain
–6 dB to +26 dB by Digital Gain
• Timing Generator:
– Fully Programmable V_RATE Timing by Serial
I/O
– Default Timing Supports Standard
Operation
– Flexible V_RATE Pin Assignment
– HD/VD Master or Slave Mode
– External Trigger, Strobe Function Support
– Flexible Draft or Pixel Summing Operation
• RG and HG Driver:
– Programmable Drivability Control
– Two Horizontal Transfer Independent
Drivers
– One Reset Gate Driver
• CCD Horizontal High-Speed Clock Phase
Control:
– Fine Step: 0.28 ns
– Wide Step: 1/3 Pixel Rate
• Vertical CCD Driver:
– 8-Channel V_DRIVER with Sub-Driver
– Supports Three-Field CCD Driving
– Three Level Drivers (V_TRANSFER) × 5
– Two Level Drivers (V_TRANSFER) × 3
– Two Level Drivers (E_SHUTTER) × 1
– 450 pF to 1890 pF with 60 Ω to 240 Ω
• Flexible Voltage Operation:
– AFET + TG: 2.7 V to 3.6 V
– VL: –5.0 V to –9.0 V
– VM: GND
– VH: 11.5 V to 15.5 V
– Low Power: 139 mW at 3.0 V, 36 MHz
– Stand-By + Power-Save Mode: 36 mW
– Stand-By Mode (MCK Off): 10 mW
• BGA-100 Package
DESCRIPTION
The VSP01M01 and VSP01M02 are complete
mixed-signal ICs for charge-coupled device (CCD)
signal processing with a built-in CCD timing
generator, analog-to-digital converter (ADC), and
CCD vertical driver. The AFE CCD channel has
correlated double sampling to extract image
information from the CCD output signal. Signal paths
have gains ranging from –9 dB to +44 dB. The black
level clamping circuit enables accurate black
reference level and quick black level recovery after
gain changes. An input signal clamp with CDS offset
adjustment function is available. The system
synchronizes the master clock, horizontal driver (HD),
and vertical driver (VD). The VSP01M01 and
VSP01M02 support all signal terminals required by
CCD architecture. The RG driver, HG driver, and
vertical driver synchronize the ADC clock phase in
order to realize ideal performance.
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated