TWL92230 Datasheet, PDF (74/141 Pages) Texas Instruments – ENERGY MANAGEMENT DEVICE COMPANION DEVICE FOR OMAP24xx

Digital Control System (DCS)
Scale Voltage Down
VMODE
TWL92230
Settings
ROOF = 1.3 V
FLOOR= 1.05 V
Core Voltage
1.3 V
1.05 V
DcDc and
LDOs Possible
States
On
Sleep
On
Sleep
Sleep if Linked to
VMODE state
Figure 10−5. VMODE Voltage Scaling Down
10.2 Host Control Outputs
10.2.1 nRESPWRON
nRESPWRON is the output reset signal delivered to the application processor at power on. This active low
signal indicates that the power-on sequence is complete. This signal must be held low for sufficient time to
allow relevant Application Processor blocks to be operational. See Table 10−7 for timing information.
10.2.2 INT
The interrupt line (INT) is an output from TWL92230 that is used to warn the application processor (active low
assertion) that an unmasked interrupt is pending. The application processor can then query the
INT_STATUS1 and INT_STATUS2 registers via I²C to identify the responsible event. The detected events are
maskable with INT_MASK1 and INT_MASK2 registers, and the events are cleared by writing to the INT_ACK1
and INT_ACK2 registers. The exact interrupt policy management is detailed in the programming model
section.
10.2.3 PWROK
During a power-up sequence, this active high signal indicates that all required regulators are powered up. In
addition, during the normal operation, when HW_nSW=1, PWROK is asserted low during a voltage transition
on VCORE.
10.3 General-Purpose I/O Port
These three input/output ports can be used for general interface signals.
Alternatively, GPIO2 and GPIO3 can be configured as SLOT_SEL and nSLEEP , respectively.
10.3.1 GPIO1
The GPIO1 becomes an input or output (according to the GPIO_DIR(1) bit in the GPIO_CTRL register. This
terminal can be left open if the GPIO_DIR(1) bit is set to 0 (GPIO1 is configured as an output).
66 SWPS021D
June 2007