TWL92230 Datasheet, PDF (50/141 Pages) Texas Instruments – ENERGY MANAGEMENT DEVICE COMPANION DEVICE FOR OMAP24xx

Memory Card Transceivers (MCT)
Similar pullup/pulldown bits for Slot 2 are shown below:
REGISTER BIT
S2_CMD_EN
S2_DAT3_EN
S2_DAT2_EN
S2_DAT1_EN
S2_DAT0_EN
S2_CMD_UP
S2_DAT3_UP
S2_DAT2_UP
S2_DAT1_UP
S2_DAT0_UP
Table 8−8. Register Bits for Slot 2
DESCRIPTION
1 = Enable pullup/pulldown on MC.S2CMD pin
1 = Enable pullup/pulldown on MC.S2DAT3 pin
1 = Enable pullup/pulldown on MC.S2DAT2 pin
1 = Enable pullup/pulldown on MC.S2DAT1 pin
1 = Enable pullup/pulldown on MC.S2DAT0 pin
For MC.S2CMD pin,
0 = Pulldown resistor selected
1 = Pullup resistor selected
For MC.S2DAT3 pin,
0 = Pulldown resistor selected
1 = Pullup resistor selected
For MC.S2DAT2 pin,
0 = Pulldown resistor selected
1 = Pullup resistor selected
For MC.S2DAT1 pin,
0 = Pulldown resistor selected
1 = Pullup resistor selected
For MC.S2DAT0 pin,
0 = Pulldown resistor selected
1 = Pullup resistor selected
8.13 DAT1 Interrupt Support
For devices/cards of Slot 1 and/or Slot 2 where DAT₁ can be used to generate an interrupt, support is included
for this via relevant I²C registers and the INT pin of TWL92230. The design of the I²C system will be such that
only an unselected, powered slot with such a device can generate this interrupt, provided that this option is
selected by the application software (this interrupt function enabled). For such a case, the individual IRQ status
is set to active (HIGH) when there is a low (GND) level on DAT1, that will be level sensitive (instead of edge
sensitive) and not debounced. The IRQ status changes to inactive (LOW) when this interrupt function is
disabled. All such interrupts are to be asynchronous. The register bits associated with this interrupt generation
function are described below:
REGISTER BIT
S1_DAT1_ST
S2_DAT1_ST
Table 8−9. DAT1 Interrupt Raw
DESCRIPTION
Mirrors the raw state on the MC.S1DAT1 pin
Mirrors the raw state on the MC.S2DAT1 pin
REGISTER BIT
S1D1_MSK
S2D1_MSK
Table 8−10. DAT1 Interrupt Mask
DESCRIPTION
Mask for Slot1 MC.S1DAT1 interrupt
Mask for Slot2 MC.S2DAT1 interrupt
REGISTER BIT
S1D1
S2D1
Table 8−11. DAT1 Interrupt Output
DESCRIPTION
High if a MC.S1DAT1 interrupt event occurred on Slot 1
High if a MC.S2DAT1 interrupt event occurred on Slot 2
42 SWPS021D
June 2007