TLV320AIC3120_16 Datasheet, PDF (74/160 Pages) Texas Instruments – TLV320AIC3120 Low-Power Mono Audio Codec With Embedded miniDSP and Mono Class-D Speaker Amplifier

TLV320AIC3120
SLAS653B – FEBRUARY 2010 – REVISED AUGUST 2016
www.ti.com
WORD
CLOCK
BIT
CLOCK
DATA
LEFT CHANNEL
RIGHT CHANNEL
NNN
---
123
3 210
NNN
---
123
3 210
LD(n)
RD(n)
LD(n) = n'th sample of left channel data
RD(n) = n'th sample of right channel data
Figure 7-38. Timing Diagram for Left-Justified Mode
NNN
---
123
LD(n+1)
WORD
CLOCK
BIT
CLOCK
DATA
LEFT CHANNEL
RIGHT CHANNEL
NNN
---
123
3210
LD(n)
NNN
---
123
3210
RD(n)
LD(n) = n'th sample of left channel data
RD(n) = n'th sample of right channel data
Figure 7-39. Timing Diagram for Left-Justified Mode With Offset = 1
NNN
---
123
LD(n+1)
WORD
CLOCK
LEFT CHANNEL
RIGHT CHANNEL
BIT
CLOCK
DATA
NN N
-- -
123
3210
NN N
-- -
123
3210
NN N
-- -
3
123
LD (n)
LD(n) = n'th sample of left channel data
RD(n)
RD(n) = n'th sample of right channel data
LD (n+1)
Figure 7-40. Timing Diagram for Left-Justified Mode With Offset = 0 and Inverted Bit Clock
For the left-justified mode, the number of bit clocks per frame should be greater-than or equal-to twice the
programmed word length of the data. Also, the programmed offset value should be less than the number
of bit clocks per frame by at least the programmed word length of the data.
7.3.15.1.3 I²S Mode
The audio interface of the TLV320AIC3120 device enters I²S mode by programming page 0 / register 27,
bits D7–D6 = to 00. In I²S mode, the MSB of the left channel is valid on the second rising edge of the bit
clock after the falling edge of the word clock. Similarly, the MSB of the right channel is valid on the second
rising edge of the bit clock after the rising edge of the word clock.
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Detailed Description
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