TLV320AIC3120_16 Datasheet, PDF (63/160 Pages) Texas Instruments – TLV320AIC3120 Low-Power Mono Audio Codec With Embedded miniDSP and Mono Class-D Speaker Amplifier

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TLV320AIC3120
SLAS653B – FEBRUARY 2010 – REVISED AUGUST 2016
If shutdown occurs because of an overcurrent condition, then the device requires a reset to re-enable the
output stage. Resetting occurs in two ways. First, the device master reset can be used, which requires
either toggling the RESET pin or using the software reset. If master reset is used, it resets all of the
registers. Second, a dedicated speaker power-stage reset can be used that keeps all of the other device
settings. The speaker power-stage reset occurs by setting page 1 / register 32, bit D7 for SPKP and
SPKM. If the fault condition has been removed, then the device returns to normal operation. If the fault is
still present, then another shutdown occurs. Repeated resetting (more than three times) is not
recommended as this could lead to overheating.
To minimize battery current leakage, the SPKVDD voltage levels must not be less than the AVDD
voltage level.
The TLV320AIC3120 device has a thermal protection (OTP) feature for the speaker drivers which is
always enabled to provide protection. If the device overheats, then the output stops switching. When the
device cools down, the device resumes switching. An overtemperature status flag is provided as a read-
only bit on page 0 / register 3, bit D1. The OTP feature is for self-protection of the device. If die
temperature can be controlled at the system or board level, then overtemperature does not occur.
7.3.12.13 Audio-Output Stage-Power Configurations
After the device has been configured (following a RESET) and the circuitry has been powered up, the
audio output stage can be powered up and powered down by register control.
These functions soft-start automatically. The two power stages can be powered up or powered down
independently..
See Table 7-34 for register control of audio output stage power configurations.
AUDIO OUTPUT PINS
HPOUT
SPKP / SPKM
Table 7-34. Audio-Output Stage-Power Configurations
DESIRED FUNCTION
Power down HPOUT driver
Power up HPOUT driver
Power down class-D drivers
Power up class-D drivers
PAGE 1 / REGISTER, BIT VALUES
Page 1 / register 31, bit D7 = 0
Page 1 / register 31, bit D7 = 1
Page 1 / register 32, bit D7 = 0
Page 1 / register 32, bit D7 = 1
7.3.12.14 DAC Setup
The following paragraphs are intended to guide a user through the steps necessary to configure the
TLV320AIC3120.
Step 1
The system clock source (master clock) and the targeted DAC sampling frequency must be identified.
Depending on the targeted performance, the decimation filter type (A, B, or C) and DOSR value can be
determined:
• Filter A should be used for 48-kHz high-performance operation; DOSR must be a multiple of 8.
• Filter B should be used for up to 96-kHz operations; DOSR must be a multiple of 4.
• Filter C should be used for up to 192-kHz operations; DOSR must be a multiple of 2.
In all cases, DOSR is limited in its range by the following condition:
2.8 MHz < DOSR × DAC_f_S < 6.2 MHz
Based on the identified filter type and the required signal-processing capabilities, the appropriate
processing block can be determined from the list of available processing blocks (PRB_P1 to PRB_P25).
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