TAS2557 Datasheet, PDF (73/110 Pages) Texas Instruments – 5.7-W Class-D Mono Audio Amplifier with Class-H Boost and Speaker Sense

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TAS2557
SLASEC2 – NOVEMBER 2016
12.3.55 ASI2_BDIV_CLK (book=0x00 page=0x01 address=0x21) [reset=1h]
Selects the BDIV clock source
Figure 100. ASI2_BDIV_CLK Register Address: 0x21
7
6
5
4
3
Reserved
RW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
2
1
0
ASI2_BDIV_SRC[2:0]
RW-1h
Table 78. ASI2 BDIV Clock Field Descriptions
Bit Field
7-3 Reserved
2-0 ASI2_BDIV_SRC[2:0]
Type
RW
RW
Reset
0h
1h
Description
Reserved
ASI1 bit clock divider (BDIV) source is
0 = NDIV_CLK (Generated On-Chip)
1 = DAC_MOD_CLK (Generated On-Chip)
2 = Reserved
3 = ADC_MOD_CLK (Generated On-Chip)
4 = ASI1_DAC_BCLK (at pin)
5 = Reserved
6 = ASI2_DAC_BCLK (at pin)
7 = Reserved
12.3.56 ASI2_BDIV_RATIO (book=0x00 page=0x01 address=0x22) [reset=2h]
Configure the BDIV ratio and power.
Figure 101. ASI2_BDIV_RATIO Register Address: 0x22
7
6
5
4
3
2
1
0
ASI2_BDIV_P
WR
ASI2_BDIV_RTO[6:0]
RW-0h
RW-2h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 79. ASI2 BDIV Ratio Field Descriptions
Bit Field
7
ASI2_BDIV_PWR
6-0 ASI2_BDIV_RTO[6:0]
Type
RW
Reset
0h
RW
2h
Description
The ASI2 BDIV divider is
0 = powered down
1 = powered up
The ASI2 BDIV ratio is
0 = 128
1=1
2=2
...
126 = 126
127 = 127
12.3.57 ASI2_WDIV_RATIO (book=0x00 page=0x01 address=0x23) [reset=20h]
Configure the WDIV ratio and power.
Figure 102. ASI2_WDIV_RATIO Register Address: 0x23
7
6
5
4
3
2
1
0
ASI2_WDIV_P
WR
ASI2_WDIV_RTO[6:0]
RW-0h
RW-20h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
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