LM3S3826 Datasheet, PDF (722/877 Pages) Texas Instruments – Stellaris® LM3S3826 Microcontroller

Universal Serial Bus (USB) Controller
16.3.1.1
Endpoints
The USB controller provides two dedicated control endpoints (IN and OUT) and 30 configurable
endpoints (15 IN and 15 OUT) that can be used for communications with a Host controller. The
endpoint number and direction associated with an endpoint is directly related to its register
designation. For example, when the Host is transmitting to endpoint 1, all configuration and data is
in the endpoint 1 transmit register interface.
Endpoint 0 is a dedicated control endpoint used for all control transactions to endpoint 0 during
enumeration or when any other control requests are made to endpoint 0. Endpoint 0 uses the first
64 bytes of the USB controller's FIFO RAM as a shared memory for both IN and OUT transactions.
The remaining 30 endpoints can be configured as control, bulk, interrupt, or isochronous endpoints.
They should be treated as 15 configurable IN and 15 configurable OUT endpoints. The endpoint
pairs are not required to have the same type for their IN and OUT endpoint configuration. For
example, the OUT portion of an endpoint pair could be a bulk endpoint, while the IN portion of that
endpoint pair could be an interrupt endpoint. The address and size of the FIFOs attached to each
endpoint can be modified to fit the application's needs.
16.3.1.2
IN Transactions
Data for IN transactions is handled through the FIFOs attached to the transmit endpoints. The sizes
of the FIFOs for the 15 configurable IN endpoints are determined by the USB Transmit FIFO Start
Address (USBTXFIFOADD) register. The maximum size of a data packet that may be placed in a
transmit endpoint’s FIFO for transmission is programmable and is determined by the value written
to the USB Maximum Transmit Data Endpoint n (USBTXMAXPn) register for that endpoint. The
endpoint’s FIFO can also be configured to use double-packet or single-packet buffering. When
double-packet buffering is enabled, two data packets can be buffered in the FIFO, which also requires
that the FIFO is at least two packets in size. When double-packet buffering is disabled, only one
packet can be buffered, even if the packet size is less than half the FIFO size.
Note: The maximum packet size set for any endpoint must not exceed the FIFO size. The
USBTXMAXPn register should not be written to while data is in the FIFO as unexpected
results may occur.
Single-Packet Buffering
If the size of the transmit endpoint's FIFO is less than twice the maximum packet size for this endpoint
(as set in the USB Transmit Dynamic FIFO Sizing (USBTXFIFOSZ) register), only one packet
can be buffered in the FIFO and single-packet buffering is required. When each packet is completely
loaded into the transmit FIFO, the TXRDY bit in the USB Transmit Control and Status Endpoint
n Low (USBTXCSRLn) register must be set. If the AUTOSET bit in the USB Transmit Control and
Status Endpoint n High (USBTXCSRHn) register is set, the TXRDY bit is automatically set when
a maximum-sized packet is loaded into the FIFO. For packet sizes less than the maximum, the
TXRDY bit must be set manually. When the TXRDY bit is set, either manually or automatically, the
packet is ready to be sent. When the packet has been successfully sent, both TXRDY and FIFONE
are cleared, and the appropriate transmit endpoint interrupt signaled. At this point, the next packet
can be loaded into the FIFO.
Double-Packet Buffering
If the size of the transmit endpoint's FIFO is at least twice the maximum packet size for this endpoint,
two packets can be buffered in the FIFO and double-packet buffering is allowed. As each packet is
loaded into the transmit FIFO, the TXRDY bit in the USBTXCSRLn register must be set. If the
AUTOSET bit in the USBTXCSRHn register is set, the TXRDY bit is automatically set when a
maximum-sized packet is loaded into the FIFO. For packet sizes less than the maximum, TXRDY
722
January 21, 2012
Texas Instruments-Production Data