TM4C1237E6PZ Datasheet, PDF (713/1306 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C1237E6PZ Microcontroller
11.5
1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x0000.0004.
3. In the GPTM Timer Mode (GPTMTnMR) register, set the TnAMS bit to 0x1, the TnCMR bit to
0x0, and the TnMR field to 0x2.
4. Configure the output state of the PWM signal (whether or not it is inverted) in the TnPWML field
of the GPTM Control (GPTMCTL) register.
5. If a prescaler is to be used, write the prescale value to the GPTM Timer n Prescale Register
(GPTMTnPR).
6. If PWM interrupts are used, configure the interrupt condition in the TnEVENT field in the
GPTMCTL register and enable the interrupts by setting the TnPWMIE bit in the GPTMTnMR
register. Note that edge detect interrupt behavior is reversed when the PWM output is inverted
(see page 725).
7. Load the timer start value into the GPTM Timer n Interval Load (GPTMTnILR) register.
8. Load the GPTM Timer n Match (GPTMTnMATCHR) register with the match value.
9. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and begin
generation of the output PWM signal.
In PWM Time mode, the timer continues running after the PWM signal has been generated. The
PWM period can be adjusted at any time by writing the GPTMTnILR register, and the change takes
effect at the next cycle after the write.
Register Map
Table 11-12 on page 714 lists the GPTM registers. The offset listed is a hexadecimal increment to
the register's address, relative to that timer's base address:
■ 16/32-bit Timer 0: 0x4003.0000
■ 16/32-bit Timer 1: 0x4003.1000
■ 16/32-bit Timer 2: 0x4003.2000
■ 16/32-bit Timer 3: 0x4003.3000
■ 16/32-bit Timer 4: 0x4003.4000
■ 16/32-bit Timer 5: 0x4003.5000
■ 32/64-bit Wide Timer 0: 0x4003.6000
■ 32/64-bit Wide Timer 1: 0x4003.7000
■ 32/64-bit Wide Timer 2: 0x4004.C000
■ 32/64-bit Wide Timer 3: 0x4004.D000
■ 32/64-bit Wide Timer 4: 0x4004.E000
■ 32/64-bit Wide Timer 5: 0x4004.F000
The SIZE field in the GPTM Peripheral Properties (GPTMPP) register identifies whether a module
has a 16/32-bit or 32/64-bit wide timer.
Note that the GP Timer module clock must be enabled before the registers can be programmed
(see page 329 or page 347). There must be a delay of 3 system clocks after the Timer module clock
is enabled before any Timer module registers are accessed.
June 12, 2014
713
Texas Instruments-Production Data